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CAT5259

更新时间: 2024-11-26 11:53:43
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安森美 - ONSEMI /
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16页 268K
描述
Quad Digitally Programmable Potentiometers (DPP™) with 256 Taps and I²C Interface

CAT5259 数据手册

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CAT5259  
Quad Digitally Programmable Potentiometers  
(DPP™) with 256 Taps and I²C Interface  
FEATURES  
DESCRIPTION  
„ Four linear taper digitally programmable  
The CAT5259 is four digitally programmable poten–  
tiometers (DPPs™) integrated with control logic and  
16 bytes of NVRAM memory. Each DPP consists of a  
series of resistive elements connected between two  
externally accessible end points. The tap points  
between each resistive element are connected to the  
wiper outputs with CMOS switches. A separate 8-bit  
control register (WCR) independently controls the  
wiper tap switches for each DPP. Associated with  
each wiper control register are four 8-bit non-volatile  
memory data registers (DR) used for storing up to four  
wiper settings. Writing to the wiper control register or  
any of the non-volatile data registers is via a I²C serial  
bus. On power-up, the contents of the first data  
register (DR0) for each of the four potentiometers  
is automatically loaded into its respective wiper  
control registers.  
potentiometers  
„ 256 resistor taps per potentiometer  
„ End to end resistance 50 kor 100 kΩ  
„ Potentiometer control and memory access via  
I²C interface  
„ Low wiper resistance, typically 100 Ω  
„ Nonvolatile memory storage for up to four  
wiper settings for each potentiometer  
„ Automatic recall of saved wiper settings at  
power up  
„ 2.5 to 6.0 volt operation  
„ Standby current less than 1 µA  
„ 1,000,000 nonvolatile WRITE cycles  
„ 100 year nonvolatile memory data retention  
„ 24-lead SOIC and 24-lead TSSOP packages  
„ Industrial temperature range  
The CAT5259 can be used as a potentiometer or as a  
two terminal, variable resistor. It is intended for circuit  
level or system level adjustments in a wide variety of  
applications. It is available in the 0ºC to 70ºC  
commercial and -40ºC to 85ºC industrial operating  
temperature ranges and offered in a 24-lead SOIC  
and TSSOP package.  
For Ordering Information details, see page 15.  
FUNCTIONAL DIAGRAM  
PIN CONFIGURATION  
SOIC (W)  
TSSOP (Y)  
R
R
R
H2  
R
H3  
H0  
H1  
NC  
A0  
1
2
3
4
5
6
7
8
9
24 A3  
SCL  
SDA  
I²C BUS  
INTERFACE  
WIPER CONTROL  
REGISTERS  
R
W0  
R
W1  
R
W2  
R
W3  
23 SCL  
22 RL2  
21 RH2  
20 RW2  
19 NC  
18 GND  
17 RW1  
16 RH1  
15 RL1  
14 A1  
RW3  
RH3  
RL3  
NC  
VCC  
RLO  
RHO  
WP  
A
A
A
A
0
1
2
3
NONVOLATILE  
DATA  
REGISTERS  
CONTROL LOGIC  
R
R
R
L2  
R
L3  
L0  
L1  
RWO 10  
A2 11  
12  
13 SDA  
© 2009 SCILLC. All rights reserved.  
Characteristics subject to change without notice  
1
Doc. No. MD-2000 Rev. J  

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