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CAT5251YI-50TE13

更新时间: 2024-11-25 22:54:19
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15页 97K
描述
Quad Digitally Programmable Potentiometer (DPP) with 256 Taps and SPI Interface

CAT5251YI-50TE13 数据手册

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E
CAT5251  
QuadDigitallyProgrammablePotentiometer(DPP™)with  
256 Taps and SPI Interface  
TM  
FEATURES  
Automatic recall of saved wiper settings at  
Four linear-taper digitally programmable  
power up  
potentiometers  
2.5 to 6.0 volt operation  
256 resistor taps per potentiometer  
End to end resistance 50kor 100kΩ  
Standby current less than 1µA  
1,000,000 nonvolatile WRITE cycles  
100 year nonvolatile memory data retention  
24-lead SOIC and 24-lead TSSOP  
Industrial temperature range  
Potentiometer control and memory access via  
SPI interface  
Low wiper resistance, typically 100  
Nonvolatile memory storage for up to four wiper  
settings for each potentiometer  
DESCRIPTION  
registers is via a SPI serial bus. On power-up, the  
contents of the first data register (DR0) for each of the  
four potentiometers is automatically loaded into its  
respective wiper control register.  
The CAT5251 is four Digitally Programmable  
Potentiometers (DPPs™) integrated with control logic  
and 16 bytes of NVRAM memory. Each DPP consists of  
a series of resistive elements connected between two  
externallyaccessibleendpoints.Thetappointsbetween  
eachresistiveelementareconnectedtothewiperoutputs  
with CMOS switches. A separate 8-bit control register  
(WCR)independentlycontrolsthewipertapswitchesfor  
each DPP. Associated with each wiper control register  
are four 8-bit non-volatile memory data registers (DR)  
used for storing up to four wiper settings. Writing to the  
wiper control register or any of the non-volatile data  
The CAT5251 can be used as a potentiometer or as a  
two terminal, variable resistor. It is intended for circuit  
level or system level adjustments in a wide variety of  
applications. Itisavailableinthe-40°Cto85°Cindustrial  
operating temperature range and offered in a 24-lead  
SOIC and TSSOP package.  
FUNCTIONAL DIAGRAM  
PIN CONFIGURATION  
SOIC/TSSOP Package (J, W/U, Y)  
R
R
H3  
R
R
H2  
H1  
H0  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
HOLD  
SO  
A0  
1
SCK  
2
R
R
3
L2  
W3  
R
R
R
CS  
SCK  
SI  
W0  
W1  
W2  
W3  
WIPER  
CONTROL  
REGISTERS  
R
R
4
H2  
SPI BUS  
INTERFACE  
H3  
R
R
5
W2  
L3  
S
O
NC  
NC  
6
CAT  
5251  
V
7
GND  
CC  
R
R
8
W1  
L0  
WP  
A0  
A1  
R
R
R
9
H1  
H0  
NONVOLATILE  
DATA  
REGISTERS  
CONTROL  
LOGIC  
R
10  
11  
12  
L1  
W0  
R
HOLD  
A1  
SI  
CS  
WP  
R
R
L3  
R
R
L2  
L1  
L0  
© 2004 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Document No. 2017, Rev. D  
1

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