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CAT28F001T-12TT PDF预览

CAT28F001T-12TT

更新时间: 2024-11-26 11:56:07
品牌 Logo 应用领域
安森美 - ONSEMI 闪存
页数 文件大小 规格书
18页 113K
描述
1 Megabit CMOS Boot Block Flash Memory

CAT28F001T-12TT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP
包装说明:8 X 20 MM, TSOP-32针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.75
最长访问时间:120 ns其他特性:TOP BOOT BLOCK
启动块:TOP命令用户界面:YES
数据轮询:NO耐久性:100000 Write/Erase Cycles
JESD-30 代码:R-PDSO-G32长度:18.4 mm
内存密度:1048576 bit内存集成电路类型:FLASH
内存宽度:8湿度敏感等级:1
功能数量:1部门数/规模:1,2,1
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX8封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装等效代码:TSSOP32,.8,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:5 V编程电压:12 V
认证状态:Not Qualified座面最大高度:1.2 mm
部门规模:8K,4K,112K最大待机电流:0.000001 A
子类别:Flash Memories最大压摆率:0.03 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
切换位:NO类型:NOR TYPE
宽度:8 mmBase Number Matches:1

CAT28F001T-12TT 数据手册

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CAT28F001  
1 Megabit CMOS Boot Block  
Flash Memory  
Licensed Intel  
second source  
FEATURES  
Deep Powerdown Mode  
— 0.05 µA ICC Typical  
Fast Read Access Time: 90/120 ns  
On-Chip Address and Data Latches  
Blocked Architecture  
— 0.8 µA IPP Typical  
Hardware Data Protection  
Electronic Signature  
— One 8 KB Boot Block w/ Lock Out  
• Top or Bottom Locations  
100,000 Program/Erase Cycles and 10 Year  
Data Retention  
— Two 4 KB Parameter Blocks  
— One 112 KB Main Block  
JEDEC Standard Pinouts:  
— 32 pin DIP  
Low Power CMOS Operation  
12.0V ± 5% Programming and Erase Voltage  
Automated Program & Erase Algorithms  
High Speed Programming  
— 32 pin PLCC  
— 32 pin TSOP  
Reset/Deep Power Down Mode  
"Green" Package Options Available  
Commercial, Industrial and Automotive  
Temperature Ranges  
DESCRIPTION  
The CAT28F001 is a high speed 128K X 8 bit electrically  
erasable and reprogrammable Flash memory ideally  
suited for applications requiring in-system or after sale  
code updates.  
The CAT28F001 is designed with a signature mode  
whichallowstheusertoidentifytheICmanufacturerand  
device type. The CAT28F001 is also designed with on-  
ChipAddressLatches, DataLatches, Programmingand  
Erase Algorithms.  
The CAT28F001 has a blocked architecture with one 8  
KB Boot Block, two 4 KB Parameter Blocks and one 112  
KB Main Block. The Boot Block section can be at the top  
orbottomofthememorymapandincludesareprogram-  
ming write lock out feature to guarantee data integrity. It  
is designed to contain secure code which will bring up  
the system minimally and download code to other loca-  
tions of CAT28F001.  
The CAT28F001 is manufactured using Catalyst’s ad-  
vanced CMOS floating gate technology. It is designed  
to endure 100,000 program/erase cycles and has a data  
retention of 10 years. The device is available in JEDEC  
approved 32-pin plastic DIP, PLCC or TSOP packages.  
BLOCK DIAGRAM  
I/O –I/O  
0
7
ADDRESS  
COUNTER  
I/O BUFFERS  
WRITE STATE  
MACHINE  
ERASE VOLTAGE  
SWITCH  
STATUS  
RP  
REGISTER  
WE  
DATA  
LATCH  
SENSE  
AMP  
COMMAND  
REGISTER  
PROGRAM VOLTAGE  
SWITCH  
CE, OE LOGIC  
CE  
OE  
Y-GATING  
Y-DECODER  
A –A  
0
16  
8K-BYTE BOOT BLOCK  
4K-BYTE PARAMETER BLOCK  
4K-BYTE PARAMETER BLOCK  
112K-BYTE MAIN BLOCK  
X-DECODER  
VOLTAGE VERIFY  
SWITCH  
© 2008 SCILLC. All rights reserved.  
Characteristics subject to change without notice  
Doc. No. MD-1078, Rev. K  
1

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