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CAT28F001PI-70BT PDF预览

CAT28F001PI-70BT

更新时间: 2024-11-26 05:17:35
品牌 Logo 应用领域
CATALYST 闪存
页数 文件大小 规格书
18页 112K
描述
1 Megabit CMOS Boot Block Flash Memory

CAT28F001PI-70BT 数据手册

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Licensed Intel  
second source  
CAT28F001  
1 Megabit CMOS Boot Block Flash Memory  
FEATURES  
Deep Powerdown Mode  
Fast Read Access Time: 70/90/120/150 ns  
On-Chip Address and Data Latches  
Blocked Architecture  
— 0.05 µA ICC Typical  
— 0.8 µA IPP Typical  
Hardware Data Protection  
Electronic Signature  
100,000 Program/Erase Cycles and 10 Year  
Data Retention  
— One 8 KB Boot Block w/ Lock Out  
• Top or Bottom Locations  
— Two 4 KB Parameter Blocks  
— One 112 KB Main Block  
JEDEC Standard Pinouts:  
— 32 pin DIP  
Low Power CMOS Operation  
12.0V ± 5% Programming and Erase Voltage  
Automated Program & Erase Algorithms  
High Speed Programming  
— 32 pin PLCC  
— 32 pin TSOP  
Reset/Deep Power Down Mode  
Commercial, Industrial and Automotive  
Temperature Ranges  
DESCRIPTION  
The CAT28F001 is a high speed 128K X 8 bit electrically  
erasable and reprogrammable Flash memory ideally  
suited for applications requiring in-system or after sale  
code updates.  
The CAT28F001 is designed with a signature mode  
whichallowstheusertoidentifytheICmanufacturerand  
device type. The CAT28F001 is also designed with on-  
ChipAddressLatches, DataLatches, Programmingand  
Erase Algorithms.  
The CAT28F001 has a blocked architecture with one 8  
KB Boot Block, two 4 KB Parameter Blocks and one 112  
KB Main Block. The Boot Block section can be at the top  
orbottomofthememorymapandincludesareprogram-  
ming write lock out feature to guarantee data integrity. It  
is designed to contain secure code which will bring up  
the system minimally and download code to other loca-  
tions of CAT28F001.  
The CAT28F001 is manufactured using Catalyst’s ad-  
vanced CMOS floating gate technology. It is designed  
to endure 100,000 program/erase cycles and has a data  
retention of 10 years. The device is available in JEDEC  
approved 32-pin plastic DIP, PLCC or TSOP packages.  
BLOCK DIAGRAM  
I/O –I/O  
0
7
ADDRESS  
COUNTER  
I/O BUFFERS  
WRITE STATE  
MACHINE  
ERASE VOLTAGE  
SWITCH  
STATUS  
RP  
REGISTER  
WE  
DATA  
LATCH  
SENSE  
AMP  
COMMAND  
REGISTER  
PROGRAM VOLTAGE  
SWITCH  
CE, OE LOGIC  
CE  
OE  
Y-GATING  
Y-DECODER  
A –A  
16  
0
8K-BYTE BOOT BLOCK  
4K-BYTE PARAMETER BLOCK  
4K-BYTE PARAMETER BLOCK  
112K-BYTE MAIN BLOCK  
X-DECODER  
VOLTAGE VERIFY  
SWITCH  
28F001 F01  
© 1998 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 25071-00 2/98 F-1  
1

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