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CAT28F001P-12 PDF预览

CAT28F001P-12

更新时间: 2024-11-19 13:06:39
品牌 Logo 应用领域
CATALYST 闪存
页数 文件大小 规格书
18页 456K
描述
Flash, 128KX8, 120ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32

CAT28F001P-12 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:DIP
包装说明:0.600 INCH, PLASTIC, DIP-32针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.29
最长访问时间:120 ns其他特性:DEEP POWER-DOWN
JESD-30 代码:R-PDIP-T32JESD-609代码:e0
长度:42.037 mm内存密度:1048576 bit
内存集成电路类型:FLASH内存宽度:8
功能数量:1端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):240编程电压:12 V
认证状态:Not Qualified座面最大高度:5.08 mm
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30类型:NOR TYPE
宽度:15.24 mmBase Number Matches:1

CAT28F001P-12 数据手册

 浏览型号CAT28F001P-12的Datasheet PDF文件第2页浏览型号CAT28F001P-12的Datasheet PDF文件第3页浏览型号CAT28F001P-12的Datasheet PDF文件第4页浏览型号CAT28F001P-12的Datasheet PDF文件第5页浏览型号CAT28F001P-12的Datasheet PDF文件第6页浏览型号CAT28F001P-12的Datasheet PDF文件第7页 
E
CAT28F001  
Licensed Intel  
second source  
1 Megabit CMOS Boot Block Flash Memory  
TM  
FEATURES  
I Deep Powerdown Mode  
I Fast Read Access Time: 90/120 ns  
I On-Chip Address and Data Latches  
I Blocked Architecture  
— 0.05 µA ICC Typical  
— 0.8 µA IPP Typical  
I Hardware Data Protection  
I Electronic Signature  
— One 8 KB Boot Block w/ Lock Out  
• Top or Bottom Locations  
I 100,000 Program/Erase Cycles and 10 Year  
Data Retention  
— Two 4 KB Parameter Blocks  
— One 112 KB Main Block  
I JEDEC Standard Pinouts:  
— 32 pin DIP  
I Low Power CMOS Operation  
I 12.0V 5% Programming and Erase Voltage  
I Automated Program & Erase Algorithms  
I High Speed Programming  
— 32 pin PLCC  
— 32 pin TSOP  
I Reset/Deep Power Down Mode  
I "Green" Package Options Available  
I Commercial, Industrial and Automotive  
Temperature Ranges  
DESCRIPTION  
The CAT28F001 is a high speed 128K X 8 bit electrically  
erasable and reprogrammable Flash memory ideally  
suited for applications requiring in-system or after sale  
code updates.  
The CAT28F001 is designed with a signature mode  
whichallowstheusertoidentifytheICmanufacturerand  
device type. The CAT28F001 is also designed with on-  
ChipAddressLatches, DataLatches, Programmingand  
Erase Algorithms.  
The CAT28F001 has a blocked architecture with one 8  
KB Boot Block, two 4 KB Parameter Blocks and one 112  
KB Main Block. The Boot Block section can be at the top  
orbottomofthememorymapandincludesareprogram-  
ming write lock out feature to guarantee data integrity. It  
is designed to contain secure code which will bring up  
the system minimally and download code to other loca-  
tions of CAT28F001.  
The CAT28F001 is manufactured using Catalyst’s ad-  
vanced CMOS floating gate technology. It is designed  
to endure 100,000 program/erase cycles and has a data  
retention of 10 years. The device is available in JEDEC  
approved 32-pin plastic DIP, PLCC or TSOP packages.  
BLOCK DIAGRAM  
I/O –I/O  
0
7
ADDRESS  
COUNTER  
I/O BUFFERS  
WRITE STATE  
MACHINE  
ERASE VOLTAGE  
SWITCH  
STATUS  
RP  
REGISTER  
WE  
DATA  
LATCH  
SENSE  
AMP  
COMMAND  
REGISTER  
PROGRAM VOLTAGE  
SWITCH  
CE, OE LOGIC  
CE  
OE  
Y-GATING  
Y-DECODER  
A –A  
0
16  
8K-BYTE BOOT BLOCK  
4K-BYTE PARAMETER BLOCK  
4K-BYTE PARAMETER BLOCK  
112K-BYTE MAIN BLOCK  
X-DECODER  
VOLTAGE VERIFY  
SWITCH  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1078, Rev. I  
1

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