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CAT28C65BG-15T PDF预览

CAT28C65BG-15T

更新时间: 2024-10-27 05:08:39
品牌 Logo 应用领域
CATALYST 存储内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
13页 418K
描述
64K-Bit CMOS PARALLEL EEPROM

CAT28C65BG-15T 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFJ包装说明:QCCJ, LDCC32,.5X.6
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.02最长访问时间:150 ns
命令用户界面:NO数据轮询:YES
耐久性:100000 Write/Erase CyclesJESD-30 代码:R-PQCC-J32
JESD-609代码:e3长度:13.965 mm
内存密度:65536 bit内存集成电路类型:EEPROM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:32
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8KX8
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC32,.5X.6封装形状:RECTANGULAR
封装形式:CHIP CARRIER页面大小:32 words
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V编程电压:5 V
认证状态:Not Qualified就绪/忙碌:YES
座面最大高度:3.55 mm最大待机电流:0.0001 A
子类别:EEPROMs最大压摆率:0.03 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40切换位:YES
宽度:11.425 mm最长写入周期时间 (tWC):5 ms
Base Number Matches:1

CAT28C65BG-15T 数据手册

 浏览型号CAT28C65BG-15T的Datasheet PDF文件第2页浏览型号CAT28C65BG-15T的Datasheet PDF文件第3页浏览型号CAT28C65BG-15T的Datasheet PDF文件第4页浏览型号CAT28C65BG-15T的Datasheet PDF文件第5页浏览型号CAT28C65BG-15T的Datasheet PDF文件第6页浏览型号CAT28C65BG-15T的Datasheet PDF文件第7页 
E
CAT28C65B  
64K-Bit CMOS PARALLEL EEPROM  
TM  
FEATURES  
I Fast read access times:  
I Commercial, industrial and automotive  
– 90/120/150ns  
temperature ranges  
I Low power CMOS dissipation:  
– Active: 25 mA max.  
I Automatic page write operation:  
– 1 to 32 bytes in 5ms  
– Standby: 100 µA max.  
– Page load timer  
I Simple write operation:  
I End of write detection:  
– Toggle bit  
– On-chip address and data latches  
– Self-timed write cycle with auto-clear  
DATA polling  
– RDY/BUSY  
I Fast write cycle time:  
– 5ms max  
I 100,000 program/erase cycles  
I 100 year data retention  
I CMOS and TTL compatible I/O  
I Hardware and software write protection  
DESCRIPTION  
The CAT28C65B is a fast, low power, 5V-only CMOS  
parallel EEPROM organized as 8K x 8-bits. It requires a  
simple interface for in-system programming. On-chip  
address and data latches, self-timed write cycle with  
auto-clear and VCC power up/down write protection  
eliminate additional timing and protection hardware.  
DATA Polling, a RDY/BUSY pin and Toggle status bits  
signal the start and end of the self-timed write cycle.  
Additionally, the CAT28C65B features hardware and  
software write protection.  
The CAT28C65B is manufactured using Catalyst’s  
advancedCMOSfloatinggatetechnology.Itisdesigned  
to endure 100,000 program/erase cycles and has a data  
retentionof100years.ThedeviceisavailableinJEDEC-  
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-  
pin PLCC packages.  
BLOCK DIAGRAM  
8,192 x 8  
EEPROM  
ARRAY  
ROW  
DECODER  
ADDR. BUFFER  
& LATCHES  
A A  
5
12  
INADVERTENT  
WRITE  
PROTECTION  
HIGH VOLTAGE  
GENERATOR  
32 BYTE PAGE  
REGISTER  
V
CC  
CE  
OE  
WE  
CONTROL  
LOGIC  
I/O BUFFERS  
DATA POLLING,  
TOGGLE BIT &  
TIMER  
RDY/BUSY LOGIC  
I/O I/O  
0
7
ADDR. BUFFER  
& LATCHES  
A A  
COLUMN  
DECODER  
0
4
RDY/BUSY  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1009, Rev. E  
1

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