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CAT28C512HNA-15T PDF预览

CAT28C512HNA-15T

更新时间: 2024-10-27 02:56:55
品牌 Logo 应用领域
CATALYST 存储内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
10页 101K
描述
512K-Bit CMOS PARALLEL E2PROM

CAT28C512HNA-15T 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:QFJ包装说明:QCCJ,
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.11Is Samacsys:N
最长访问时间:150 ns其他特性:100000 PROGRAM/ERASE CYCLES; DATA RETENTION = 100 YEARS
数据保留时间-最小值:100JESD-30 代码:R-PQCC-J32
JESD-609代码:e0长度:13.97 mm
内存密度:524288 bit内存集成电路类型:EEPROM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:32
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:105 °C
最低工作温度:-40 °C组织:64KX8
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):240
编程电压:5 V认证状态:Not Qualified
座面最大高度:3.55 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:11.43 mmBase Number Matches:1

CAT28C512HNA-15T 数据手册

 浏览型号CAT28C512HNA-15T的Datasheet PDF文件第2页浏览型号CAT28C512HNA-15T的Datasheet PDF文件第3页浏览型号CAT28C512HNA-15T的Datasheet PDF文件第4页浏览型号CAT28C512HNA-15T的Datasheet PDF文件第5页浏览型号CAT28C512HNA-15T的Datasheet PDF文件第6页浏览型号CAT28C512HNA-15T的Datasheet PDF文件第7页 
Advanced  
CAT28C512/513  
512K-Bit CMOS PARALLEL E2PROM  
FEATURES  
Fast Read Access Times: 120/150 ns  
Automatic Page Write Operation:  
–1 to 128 Bytes in 5ms  
Low Power CMOS Dissipation:  
–Active: 50 mA Max.  
–Page Load Timer  
–Standby: 200 µA Max.  
End of Write Detection:  
–Toggle Bit  
Simple Write Operation:  
DATA Polling  
–On-Chip Address and Data Latches  
–Self-Timed Write Cycle with Auto-Clear  
Hardware and Software Write Protection  
100,000 Program/Erase Cycles  
100 Year Data Retention  
Fast Write Cycle Time:  
–5ms Max  
CMOS and TTL Compatible I/O  
Commercial, Industrial and Automotive  
Temperature Ranges  
DESCRIPTION  
The CAT28C512/513 is manufactured using Catalyst’s  
advancedCMOSfloatinggatetechnology.Itisdesigned  
to endure 100,000 program/erase cycles and has a data  
retention of 100 years. The device is available in JEDEC  
approved 32-pin DIP, PLCC, 32-pin TSOP and 40-pin  
TSOP packages.  
TheCAT28C512/513isafast,lowpower,5V-onlyCMOS  
parallel E2PROM organized as 64K x 8-bits. It requires  
a simple interface for in-system programming. On-chip  
address and data latches, self-timed write cycle with  
auto-clear and VCC power up/down write protection  
eliminate additional timing and protection hardware.  
DATA Polling and Toggle status bits signal the start and  
end of the self-timed write cycle. Additionally, the  
CAT28C512/513 features hardware and software write  
protection.  
BLOCK DIAGRAM  
65,536 x 8  
E2PROM  
ARRAY  
ROW  
DECODER  
ADDR. BUFFER  
A –A  
7
15  
& LATCHES  
INADVERTENT  
WRITE  
PROTECTION  
HIGH VOLTAGE  
GENERATOR  
128 BYTE PAGE  
REGISTER  
V
CC  
CE  
OE  
WE  
CONTROL  
TIMER  
I/O BUFFERS  
DATA POLLING  
AND  
TOGGLE BIT  
I/O –I/O  
0
7
ADDR. BUFFER  
& LATCHES  
A –A  
COLUMN  
DECODER  
0
6
5096 FHD F02  
© 1998 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 25074-00 2/98  
1

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