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CAT28C257GI-12T PDF预览

CAT28C257GI-12T

更新时间: 2024-10-27 03:08:55
品牌 Logo 应用领域
CATALYST 存储内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 523K
描述
256K-Bit CMOS PARALLEL EEPROM

CAT28C257GI-12T 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFJ包装说明:QCCJ, LDCC32,.5X.6
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.1最长访问时间:120 ns
命令用户界面:NO数据轮询:YES
耐久性:100000 Write/Erase CyclesJESD-30 代码:R-PQCC-J32
JESD-609代码:e3长度:13.97 mm
内存密度:262144 bit内存集成电路类型:EEPROM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:32
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX8
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC32,.5X.6封装形状:RECTANGULAR
封装形式:CHIP CARRIER页面大小:128 words
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V编程电压:5 V
认证状态:Not Qualified座面最大高度:3.55 mm
最大待机电流:0.00015 A子类别:EEPROMs
最大压摆率:0.03 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
切换位:YES宽度:11.43 mm
最长写入周期时间 (tWC):5 msBase Number Matches:1

CAT28C257GI-12T 数据手册

 浏览型号CAT28C257GI-12T的Datasheet PDF文件第2页浏览型号CAT28C257GI-12T的Datasheet PDF文件第3页浏览型号CAT28C257GI-12T的Datasheet PDF文件第4页浏览型号CAT28C257GI-12T的Datasheet PDF文件第5页浏览型号CAT28C257GI-12T的Datasheet PDF文件第6页浏览型号CAT28C257GI-12T的Datasheet PDF文件第7页 
E
CAT28C257  
256K-Bit CMOS PARALLEL EEPROM  
TM  
FEATURES  
Automatic page write operation:  
–1 to 128 Bytes in 5ms  
–Page load timer  
Fast read access times: 120/150 ns  
Low power CMOS dissipation:  
–Active: 25 mA max.  
End of write detection:  
–Toggle bit  
–Standby: 150 µA max.  
Simple write operation:  
DATA polling  
–On-chip address and data latches  
–Self-timed write cycle with auto-clear  
Hardware and software write protection  
100,000 Program/erase cycles  
100 Year data retention  
Fast write cycle time:  
–5ms max  
CMOS and TTL compatible I/O  
Commercial, industrial and automotive  
temperature ranges  
DESCRIPTION  
The CAT28C257 is a fast, low power, 5V-only CMOS  
Parallel EEPROM organized as 32K x 8-bits. It requires a  
simple interface for in-system programming. On-chip  
addressanddatalatches,self-timedwritecyclewithauto-  
clear and VCC power up/down write protection eliminate  
additional timing and protection hardware. DATA Polling  
and Toggle status bits signal the start and end of the self-  
timed write cycle. Additionally, the CAT28C257 features  
hardware and software write protection.  
The CAT28C257 is manufactured using Catalyst’s  
advanced CMOS floating gate technology. It is designed  
to endure 100,000 program/erase cycles and has a data  
retention of 100 years. The device is available in JEDEC  
approved 28-pin DIP or 32-pin PLCC packages.  
BLOCK DIAGRAM  
32,768 x 8  
EEPROM  
ARRAY  
ROW  
DECODER  
ADDR. BUFFER  
A –A  
7
14  
& LATCHES  
INADVERTENT  
WRITE  
PROTECTION  
HIGH VOLTAGE  
GENERATOR  
128 BYTE PAGE  
REGISTER  
V
CC  
CE  
OE  
WE  
CONTROL  
LOGIC  
I/O BUFFERS  
DATA POLLING  
AND  
TIMER  
TOGGLE BIT  
I/O –I/O  
0
7
ADDR. BUFFER  
& LATCHES  
A –A  
COLUMN  
DECODER  
0
6
© 2004 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1015, Rev. D  
1

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