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CAT28C256NI-15T PDF预览

CAT28C256NI-15T

更新时间: 2024-11-19 03:06:27
品牌 Logo 应用领域
CATALYST 内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 526K
描述
256K-Bit Parallel EEPROM

CAT28C256NI-15T 数据手册

 浏览型号CAT28C256NI-15T的Datasheet PDF文件第2页浏览型号CAT28C256NI-15T的Datasheet PDF文件第3页浏览型号CAT28C256NI-15T的Datasheet PDF文件第4页浏览型号CAT28C256NI-15T的Datasheet PDF文件第5页浏览型号CAT28C256NI-15T的Datasheet PDF文件第6页浏览型号CAT28C256NI-15T的Datasheet PDF文件第7页 
E
CAT28C256  
256K-Bit Parallel EEPROM  
TM  
FEATURES  
Hardware and software write protection  
Fast read access times: 120/150ns  
Automatic page write operation:  
–1 to 64 bytes in 5ms  
Low power CMOS dissipation:  
–Active: 25 mA max  
–Page load timer  
–Standby: 150 µA max  
End of write detection:  
–Toggle bit  
Simple write operation:  
–On-chip address and data latches  
–Self-timed write cycle with auto-clear  
DATA polling  
100,000 program/erase cycles  
100 year data retention  
Fast write cycle time:  
–5ms max  
CMOS and TTL compatible I/O  
Commerical, industrial and automotive  
temperature ranges  
DESCRIPTION  
The CAT28C256 is a fast, low power, 5V-only CMOS  
parallel EEPROM organized as 32K x 8-bits. It requires a  
simple interface for in-system programming. On-chip  
addressanddatalatches,self-timedwritecyclewithauto-  
clear and VCC power up/down write protection eliminate  
additional timing and protection hardware. DATA Polling  
and Toggle status bits signal the start and end of the self-  
timed write cycle. Additionally, the CAT28C256 features  
hardware and software write protection.  
The CAT28C256 is manufactured using Catalyst’s ad-  
vancedCMOSfloatinggatetechnology. Itisdesignedto  
endure 100,000 program/erase cycles and has a data  
retention of 100 years. The device is available in JEDEC  
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC  
packages.  
BLOCK DIAGRAM  
32,768 x 8  
EEPROM  
ARRAY  
ROW  
DECODER  
ADDR. BUFFER  
A –A  
6
14  
& LATCHES  
INADVERTENT  
WRITE  
PROTECTION  
HIGH VOLTAGE  
GENERATOR  
64 BYTE PAGE  
REGISTER  
V
CC  
CE  
OE  
WE  
CONTROL  
LOGIC  
I/O BUFFERS  
DATA POLLING  
AND  
TIMER  
TOGGLE BIT  
I/O –I/O  
0
7
ADDR. BUFFER  
& LATCHES  
A –A  
COLUMN  
DECODER  
0
5
Doc. No. 1004, Rev. D  
© 2004 by Catalyst Semiconductor, Inc.  
1
Characteristics subject to change without notice  

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