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CAT28C256HPA-15T PDF预览

CAT28C256HPA-15T

更新时间: 2024-10-27 05:08:39
品牌 Logo 应用领域
CATALYST 可编程只读存储器
页数 文件大小 规格书
10页 79K
描述
32K-Bit Parallel E2PROM

CAT28C256HPA-15T 数据手册

 浏览型号CAT28C256HPA-15T的Datasheet PDF文件第2页浏览型号CAT28C256HPA-15T的Datasheet PDF文件第3页浏览型号CAT28C256HPA-15T的Datasheet PDF文件第4页浏览型号CAT28C256HPA-15T的Datasheet PDF文件第5页浏览型号CAT28C256HPA-15T的Datasheet PDF文件第6页浏览型号CAT28C256HPA-15T的Datasheet PDF文件第7页 
CAT28C256  
32K-Bit Parallel E2PROM  
FEATURES  
Hardware and Software Write Protection  
Fast Read Access Times: 120/150ns  
Automatic Page Write Operation:  
–1 to 64 Bytes in 5ms  
Low Power CMOS Dissipation:  
–Active: 25 mA Max.  
–Page Load Timer  
–Standby: 150 µA Max.  
End of Write Detection:  
–Toggle Bit  
Simple Write Operation:  
–On-Chip Address and Data Latches  
–Self-Timed Write Cycle with Auto-Clear  
–DATA Polling  
100,000 Program/Erase Cycles  
100 Year Data Retention  
Fast Write Cycle Time:  
–5ms Max  
CMOS and TTL Compatible I/O  
Commerical, Industrial and Automotive  
Temperature Ranges  
DESCRIPTION  
The CAT28C256 is a fast, low power, 5V-only CMOS  
parallel E2PROM organized as 32K x 8-bits. It requires a  
simple interface for in-system programming. On-chip  
addressanddatalatches,self-timedwritecyclewithauto-  
clear and VCC power up/down write protection eliminate  
additional timing and protection hardware. DATA Polling  
and Toggle status bits signal the start and end of the self-  
timed write cycle. Additionally, the CAT28C256 features  
hardware and software write protection.  
The CAT28C256 is manufactured using Catalyst’s ad-  
vancedCMOSfloatinggatetechnology. Itisdesignedto  
endure 100,000 program/erase cycles and has a data  
retention of 100 years. The device is available in JEDEC  
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC  
packages.  
BLOCK DIAGRAM  
32,768 x 8  
E2PROM  
ARRAY  
ROW  
DECODER  
ADDR. BUFFER  
A –A  
6
14  
& LATCHES  
INADVERTENT  
WRITE  
PROTECTION  
HIGH VOLTAGE  
GENERATOR  
64 BYTE PAGE  
REGISTER  
V
CC  
CE  
OE  
WE  
CONTROL  
LOGIC  
I/O BUFFERS  
DATA POLLING  
AND  
TIMER  
TOGGLE BIT  
I/O –I/O  
0
7
ADDR. BUFFER  
& LATCHES  
A –A  
COLUMN  
DECODER  
0
5
5096 FHD F02  
Doc. No. 25020-0A 2/98  
© 1998 by Catalyst Semiconductor, Inc.  
1
Characteristics subject to change without notice  

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