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CAT28C256HNA-12T PDF预览

CAT28C256HNA-12T

更新时间: 2024-11-26 03:42:23
品牌 Logo 应用领域
CATALYST 存储内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
10页 79K
描述
32K-Bit Parallel E2PROM

CAT28C256HNA-12T 技术参数

生命周期:Transferred零件包装代码:QFJ
包装说明:QCCJ,针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.05
Is Samacsys:N最长访问时间:120 ns
其他特性:100000 PROGRAM/ERASE CYCLESJESD-30 代码:R-PQCC-J32
长度:13.97 mm内存密度:262144 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:32
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:105 °C
最低工作温度:-40 °C组织:32KX8
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL编程电压:5 V
认证状态:Not Qualified座面最大高度:3.55 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:11.43 mm
Base Number Matches:1

CAT28C256HNA-12T 数据手册

 浏览型号CAT28C256HNA-12T的Datasheet PDF文件第2页浏览型号CAT28C256HNA-12T的Datasheet PDF文件第3页浏览型号CAT28C256HNA-12T的Datasheet PDF文件第4页浏览型号CAT28C256HNA-12T的Datasheet PDF文件第5页浏览型号CAT28C256HNA-12T的Datasheet PDF文件第6页浏览型号CAT28C256HNA-12T的Datasheet PDF文件第7页 
CAT28C256  
32K-Bit Parallel E2PROM  
FEATURES  
Hardware and Software Write Protection  
Fast Read Access Times: 120/150ns  
Automatic Page Write Operation:  
–1 to 64 Bytes in 5ms  
Low Power CMOS Dissipation:  
–Active: 25 mA Max.  
–Page Load Timer  
–Standby: 150 µA Max.  
End of Write Detection:  
–Toggle Bit  
Simple Write Operation:  
–On-Chip Address and Data Latches  
–Self-Timed Write Cycle with Auto-Clear  
–DATA Polling  
100,000 Program/Erase Cycles  
100 Year Data Retention  
Fast Write Cycle Time:  
–5ms Max  
CMOS and TTL Compatible I/O  
Commerical, Industrial and Automotive  
Temperature Ranges  
DESCRIPTION  
The CAT28C256 is a fast, low power, 5V-only CMOS  
parallel E2PROM organized as 32K x 8-bits. It requires a  
simple interface for in-system programming. On-chip  
addressanddatalatches,self-timedwritecyclewithauto-  
clear and VCC power up/down write protection eliminate  
additional timing and protection hardware. DATA Polling  
and Toggle status bits signal the start and end of the self-  
timed write cycle. Additionally, the CAT28C256 features  
hardware and software write protection.  
The CAT28C256 is manufactured using Catalyst’s ad-  
vancedCMOSfloatinggatetechnology. Itisdesignedto  
endure 100,000 program/erase cycles and has a data  
retention of 100 years. The device is available in JEDEC  
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC  
packages.  
BLOCK DIAGRAM  
32,768 x 8  
E2PROM  
ARRAY  
ROW  
DECODER  
ADDR. BUFFER  
A –A  
6
14  
& LATCHES  
INADVERTENT  
WRITE  
PROTECTION  
HIGH VOLTAGE  
GENERATOR  
64 BYTE PAGE  
REGISTER  
V
CC  
CE  
OE  
WE  
CONTROL  
LOGIC  
I/O BUFFERS  
DATA POLLING  
AND  
TIMER  
TOGGLE BIT  
I/O –I/O  
0
7
ADDR. BUFFER  
& LATCHES  
A –A  
COLUMN  
DECODER  
0
5
5096 FHD F02  
Doc. No. 25020-0A 2/98  
© 1998 by Catalyst Semiconductor, Inc.  
1
Characteristics subject to change without notice  

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