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CAT28C17ANA-20T PDF预览

CAT28C17ANA-20T

更新时间: 2024-10-26 05:08:39
品牌 Logo 应用领域
CATALYST 存储内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
8页 63K
描述
16K-Bit CMOS PARALLEL E2PROM

CAT28C17ANA-20T 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:QFJ包装说明:QCCJ, LDCC32,.5X.6
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.13Is Samacsys:N
最长访问时间:200 ns命令用户界面:NO
数据轮询:YES耐久性:10000 Write/Erase Cycles
JESD-30 代码:R-PQCC-J32JESD-609代码:e0
长度:13.97 mm内存密度:16384 bit
内存集成电路类型:EEPROM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:32字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:105 °C最低工作温度:-40 °C
组织:2KX8封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC32,.5X.6
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:5 V编程电压:5 V
认证状态:Not Qualified就绪/忙碌:YES
座面最大高度:3.55 mm最大待机电流:0.0001 A
子类别:EEPROMs最大压摆率:0.035 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30切换位:NO
宽度:11.43 mm最长写入周期时间 (tWC):10 ms
Base Number Matches:1

CAT28C17ANA-20T 数据手册

 浏览型号CAT28C17ANA-20T的Datasheet PDF文件第2页浏览型号CAT28C17ANA-20T的Datasheet PDF文件第3页浏览型号CAT28C17ANA-20T的Datasheet PDF文件第4页浏览型号CAT28C17ANA-20T的Datasheet PDF文件第5页浏览型号CAT28C17ANA-20T的Datasheet PDF文件第6页浏览型号CAT28C17ANA-20T的Datasheet PDF文件第7页 
CAT28C17A  
16K-Bit CMOS PARALLEL E2PROM  
FEATURES  
Fast Read Access Times: 200 ns  
End of Write Detection:  
DATA Polling  
Low Power CMOS Dissipation:  
–Active: 25 mA Max.  
–RDY/BSY Pin  
–Standby: 100 µA Max.  
Hardware Write Protection  
CMOS and TTL Compatible I/O  
10,000 Program/Erase Cycles  
10 Year Data Retention  
Simple Write Operation:  
–On-Chip Address and Data Latches  
–Self-Timed Write Cycle with Auto-Clear  
Fast Write Cycle Time: 10ms Max  
Commercial,Industrial and Automotive  
Temperature Ranges  
DESCRIPTION  
The CAT28C17A is a fast, low power, 5V-only CMOS  
parallel E2PROM organized as 2K x 8-bits. It requires a  
simple interface for in-system programming. On-chip  
address and data latches, self-timed write cycle with  
auto-clear and VCC power up/down write protection  
eliminate additional timing and protection hardware.  
DATA Polling and a RDY/BSY pin signal the start and  
end of the self-timed write cycle. Additionally, the  
CAT28C17A features hardware write protection.  
The CAT28C17A is manufactured using Catalyst’s ad-  
vancedCMOSfloatinggatetechnology. Itisdesignedto  
endure 10,000 program/erase cycles and has a data  
retention of 10 years. The device is available in JEDEC  
approved 28-pin DIP and SOIC or 32-pin PLCC pack-  
ages.  
BLOCK DIAGRAM  
2,048 x 8  
E2PROM  
ARRAY  
ROW  
DECODER  
ADDR. BUFFER  
A –A  
4
10  
& LATCHES  
INADVERTENT  
WRITE  
PROTECTION  
HIGH VOLTAGE  
GENERATOR  
V
CC  
CE  
OE  
WE  
CONTROL  
LOGIC  
I/O BUFFERS  
I/O –I/O  
DATA POLLING  
& RDY/BUSY  
TIMER  
0
7
ADDR. BUFFER  
& LATCHES  
A –A  
COLUMN  
DECODER  
0
3
RDY/BUSY  
5091 FHD F02  
Doc. No. 25034-00 2/98  
© 1998 by Catalyst Semiconductor, Inc.  
1
Characteristics subject to change without notice  

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