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CAT25C33GLS-1.8TE13 PDF预览

CAT25C33GLS-1.8TE13

更新时间： 2024-11-19 05:08:35
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
11页 315K
描述
32K/64K-Bit SPI Serial CMOS EEPROM

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CAT25C33GLS-1.8TE13 数据手册

 浏览型号CAT25C33GLS-1.8TE13的Datasheet PDF文件第2页浏览型号CAT25C33GLS-1.8TE13的Datasheet PDF文件第3页浏览型号CAT25C33GLS-1.8TE13的Datasheet PDF文件第4页浏览型号CAT25C33GLS-1.8TE13的Datasheet PDF文件第5页浏览型号CAT25C33GLS-1.8TE13的Datasheet PDF文件第6页浏览型号CAT25C33GLS-1.8TE13的Datasheet PDF文件第7页 
CAT25C33/65  
32K/64K-Bit SPI Serial CMOS EEPROM  
FEATURES  
■ 1,000,000 program/erase cycles  
■ 100 year data tetention  
■ 10 MHz SPI compatible  
■ 1.8 to 6.0 volt operation  
■ Self-timed write cycle  
■ Hardware and software protection  
■ Low power CMOS technology  
■ SPI modes (0,0 &1,1)  
■ 8-pin DIP/SOIC and 14-pin TSSOP  
■ 64-byte page write buffer  
■ Block write protection  
■ Commercial, industrial, automotive and extended  
– Protect first page, last page, any 1/4 or lower  
1/2 of EEPROM array  
temperature ranges  
DESCRIPTION  
required to access the device. The HOLD pin may be  
used to suspend any serial communication without  
resetting the serial sequence. The CAT25C32/64 is  
designed with software and hardware write protection  
features including Block write protection. The device is  
available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and  
20-pin TSSOP packages.  
The CAT25C33/65 is a 32K/64K-Bit SPI Serial CMOS  
EEPROM internally organized as 4Kx8/8Kx8 bits.  
Catalyst’s advanced CMOS Technology substantially  
reduces device power requirements. The CAT25C33/  
65 features a 64-byte page write buffer. The device  
operates via the SPI bus serial interface and is enabled  
thoughaChipSelect(CS). InadditiontotheChipSelect,  
the clock input (SCK), data in (SI) and data out (SO) are  
PIN CONFIGURATION  
BLOCK DIAGRAM  
SOIC Package (S, V, GV) TSSOP Package (U14, Y14)  
14  
13  
12  
11  
10  
9
8
1
2
3
4
5
6
7
VCC  
HOLD  
NC  
NC  
NC  
CS  
SO  
NC  
NC  
NC  
WP  
1
2
3
4
8
7
6
5
V
CS  
SO  
WP  
CC  
SENSE AMPS  
SHIFT REGISTERS  
HOLD  
SCK  
SI  
V
SS  
SCK  
SI  
COLUMN  
DECODERS  
WORD ADDRESS  
BUFFERS  
V
SS  
DIP Package (P, L, GL)  
1
2
3
4
8
7
6
5
V
SO  
SI  
CS  
SO  
CC  
I/O  
CONTROL  
HOLD  
SCK  
SI  
E2PROM  
ARRAY  
WP  
CS  
SPI  
CONTROL  
LOGIC  
XDEC  
V
SS  
WP  
HOLD  
SCK  
PIN FUNCTIONS  
Pin Name  
BLOCK  
PROTECT  
LOGIC  
Function  
SO  
Serial Data Output  
DATA IN  
STORAGE  
SCK  
WP  
VCC  
VSS  
CS  
Serial Clock  
Write Protect  
HIGH VOLTAGE/  
TIMING CONTROL  
+1.8V to +6.0V Power Supply  
Ground  
STATUS  
REGISTER  
Chip Select  
SI  
Serial Data Input  
Suspends Serial Input  
HOLD  
NC  
No Connect  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1000, Rev. H  
1
1234567...11

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