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CAT25C256VE-GT2 PDF预览

CAT25C256VE-GT2

更新时间： 2024-11-05 05:08:35
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 444K
描述
128K/256K-Bit SPI Serial CMOS EEPROM

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中文翻译

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CAT25C256VE-GT2 数据手册

 浏览型号CAT25C256VE-GT2的Datasheet PDF文件第2页浏览型号CAT25C256VE-GT2的Datasheet PDF文件第3页浏览型号CAT25C256VE-GT2的Datasheet PDF文件第4页浏览型号CAT25C256VE-GT2的Datasheet PDF文件第5页浏览型号CAT25C256VE-GT2的Datasheet PDF文件第6页浏览型号CAT25C256VE-GT2的Datasheet PDF文件第7页 
CAT25C128/256  
128K/256K-Bit SPI Serial CMOS EEPROM  
FEATURES  
I Self-Timed Write Cycle  
I 64-Byte Page Write Buffer  
I Block Write Protection  
I 5 MHz SPI Compatible  
I 1.8 to 5.5 Volt Operation  
I Hardware and Software Protection  
I Low Power CMOS Technology  
I SPI Modes (0,0 &1,1)  
– Protect 1/4, 1/2 or all of EEPROM Array  
I 100,000 Program/Erase Cycles  
I 100 Year Data Retention  
I Industrial and Automotive  
I RoHS-compliant packages  
Temperature Ranges  
DESCRIPTION  
The CAT25C128/256 is a 128K/256K-Bit SPI Serial  
CMOS EEPROM internally organized as 16Kx8/32Kx8  
bits. Catalyst’s advanced CMOS Technology  
substantially reduces device power requirements. The  
CAT25C128/256 features a 64-byte page write buffer.  
The device operates via the SPI bus serial interface  
and is enabled through a Chip Select (CS). In addition  
to the Chip Select, the clock input (SCK), data in (SI)  
and data out (SO) are required to access the device.  
The HOLD pin may be used to suspend any serial  
communication without resetting the serial sequence.  
The CAT25C128/256 is designed with software and  
hardware write protection features including Block Lock  
protection. The device is available in 8-pin DIP, 8-pin  
SOIC, 14-pin TSSOP and 20-pin TSSOP packages.  
PIN CONFIGURATION  
BLOCK DIAGRAM  
TSSOP Package (Y14)**  
SOIC Package  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
CS  
(V**, X)  
V
SENSE AMPS  
SHIFT REGISTERS  
CC  
SO  
NC  
NC  
NC  
WP  
HOLD  
NC  
NC  
NC  
SCK  
SI  
1
2
3
4
8
7
6
5
V
CS  
SO  
WP  
CC  
HOLD  
SCK  
SI  
COLUMN  
DECODERS  
WORD ADDRESS  
BUFFERS  
V
SS  
V
8
SS  
TSSOP Package (Y20)**  
DIP Package (L)  
SO  
SI  
I/O  
CONTROL  
1
2
3
4
5
6
20  
19  
18  
17  
16  
NC  
CS  
NC  
1
2
3
4
8
7
6
5
V
CS  
SO  
CC  
V
CC  
CS  
EEPROM  
ARRAY  
HOLD  
SCK  
SI  
SPI  
CONTROL  
LOGIC  
XDEC  
HOLD  
HOLD  
NC  
SO  
SO  
NC  
NC  
WP  
WP  
WP  
SS  
HOLD  
SCK  
15  
14  
13  
12  
11  
NC  
SCK  
7
**CAT25C128 only.  
BLOCK  
PROTECT  
LOGIC  
V
SI  
NC  
NC  
8
SS  
NC  
NC  
9
10  
DATA IN  
STORAGE  
PIN FUNCTIONS  
Pin Name  
SO  
Function  
Serial data Output  
Serial Clock  
Write Protect  
Power Supply  
Ground  
HIGH VOLTAGE/  
TIMING CONTROL  
SCK  
WP  
VCC  
STATUS  
REGISTER  
VSS  
CS  
Chip Select  
SI  
HOLD  
NC  
Serial Data Input  
Suspends Serial Input  
No Connect  
For Ordering Information details, see page 11.  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Document No. 1018, Rev. I  
1
1234567...12

中文翻译

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