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CAT25640VI-GT3 PDF预览

CAT25640VI-GT3

更新时间: 2024-11-06 02:52:51
品牌 Logo 应用领域
CATALYST 内存集成电路光电二极管PC可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
16页 234K
描述
64-Kb SPI Serial CMOS EEPROM

CAT25640VI-GT3 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOIC
包装说明:0.150 INCH, GREEN, MS-012, SOIC-8针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.44
最大时钟频率 (fCLK):10 MHzJESD-30 代码:R-PDSO-G8
JESD-609代码:e4长度:4.9 mm
内存密度:65536 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:8字数:8192 words
字数代码:8000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:8KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.75 mm串行总线类型:SPI
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm
最长写入周期时间 (tWC):5 msBase Number Matches:1

CAT25640VI-GT3 数据手册

 浏览型号CAT25640VI-GT3的Datasheet PDF文件第2页浏览型号CAT25640VI-GT3的Datasheet PDF文件第3页浏览型号CAT25640VI-GT3的Datasheet PDF文件第4页浏览型号CAT25640VI-GT3的Datasheet PDF文件第5页浏览型号CAT25640VI-GT3的Datasheet PDF文件第6页浏览型号CAT25640VI-GT3的Datasheet PDF文件第7页 
CAT25640  
64-Kb SPI Serial CMOS EEPROM  
FEATURES  
DESCRIPTION  
„ 10 MHz SPI compatible  
The CAT25640 is a 64-Kb Serial CMOS EEPROM  
device internally organized as 8Kx8 bits. This features  
a 64-byte page write buffer and supports the Serial  
Peripheral Interface (SPI) protocol. The device is  
„ 1.8V to 5.5V supply voltage range  
„ SPI modes (0,0) & (1,1)  
¯¯  
„ 64-byte page write buffer  
enabled through a Chip Select (CS) input. In addition,  
the required bus signals are clock input (SCK), data  
„ Self-timed write cycle  
¯¯¯¯¯  
input (SI) and data output (SO) lines. The HOLD input  
„ Hardware and software protection  
„ Block write protection  
may be used to pause any serial communication with  
the CAT25640 device. The device features software  
and hardware write protection, including partial as  
well as full array protection.  
– Protect 1/4, 1/2 or entire EEPROM array  
„ Low power CMOS technology  
„ 1,000,000 program/erase cycles  
„ 100 year data retention  
„ Industrial temperature range  
„ RoHS-compliant 8 lead PDIP, SOIC, TSSOP and  
8-pad TDFN packages  
PIN CONFIGURATION  
FUNCTIONAL SYMBOL  
VCC  
PDIP (L)  
SOIC (V)  
TSSOP (Y)  
TDFN (VP2)  
SI  
¯¯  
1
2
3
4
8
7
6
5
VCC  
CS  
CS  
SO  
CAT25640  
WP  
HOLD  
SCK  
¯¯¯¯¯  
HOLD  
SO  
¯¯¯  
WP  
SCK  
SI  
VSS  
VSS  
PIN FUNCTION  
Pin Name  
Function  
¯¯  
CS  
Chip Select  
For Ordering Information details, see page 15.  
SO  
Serial Data Output  
Write Protect  
¯¯¯  
WP  
VSS  
SI  
Ground  
Serial Data Input  
Serial Clock  
SCK  
¯¯¯¯¯  
Hold Transmission Input  
Power Supply  
HOLD  
VCC  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
1
Doc. No. MD-1128 Rev. B  

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