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CAT25020GZ-TE13REV-C PDF预览

CAT25020GZ-TE13REV-C

更新时间： 2024-11-22 07:34:59
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
页数 文件大小 规格书
11页 114K
描述
256X8 SPI BUS SERIAL EEPROM, PDSO8, ROHS COMPLIANT, MSOP-8

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中文翻译

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CAT25020GZ-TE13REV-C 数据手册

 浏览型号CAT25020GZ-TE13REV-C的Datasheet PDF文件第2页浏览型号CAT25020GZ-TE13REV-C的Datasheet PDF文件第3页浏览型号CAT25020GZ-TE13REV-C的Datasheet PDF文件第4页浏览型号CAT25020GZ-TE13REV-C的Datasheet PDF文件第5页浏览型号CAT25020GZ-TE13REV-C的Datasheet PDF文件第6页浏览型号CAT25020GZ-TE13REV-C的Datasheet PDF文件第7页 
CAT25010/20/40  
1K/2K/4K SPI Serial CMOS EEPROM  
FEATURES  
■ 1,000,000 program/erase cycles  
■ 100 year data retention  
■ 10 MHz SPI compatible  
■ 1.8 to 5.5 volt operation  
■ Self-timed write cycle  
■ Hardware and software protection  
■ Low power CMOS technology  
■ SPI modes (0,0 & 1,1)  
■ 8-Pin DIP/SOIC, 8-Pin TSSOP and 8-Pin MSOP  
■ 16-byte page write buffer  
■ Block write protection  
■ Commercial, industrial, automotive and extended  
– Protect 1/4, 1/2 or all of EEPROM array  
temperature ranges  
DESCRIPTION  
Chip Select, the clock input (SCK), data in (SI) and data  
out (SO) are required to access the device. The HOLD  
pin may be used to suspend any serial communication  
without resetting the serial sequence. The CAT25010/  
20/40 is designed with software and hardware write  
protectionfeaturesincludingBlockWriteprotection.The  
deviceisavailablein8-pinDIP, 8-pinSOIC, 8-pinMSOP  
and 8-pin TSSOP packages.  
The CAT25010/20/40 is a 1K/2K/4K Bit SPI Serial  
CMOS EEPROM internally organized as 128x8/256x8/  
512x8 bits. Catalyst’s advanced CMOS Technology  
substantially reduces device power requirements. The  
CAT25010/20/40 features a 16-byte page write buffer.  
The device operates via the SPI bus serial interface and  
is enabled though a Chip Select (CS). In addition to the  
PIN CONFIGURATION  
BLOCK DIAGRAM  
SOIC Package (S, V, GV)  
MSOP Package (R, Z, GZ)  
SENSE AMPS  
SHIFT REGISTERS  
1
2
3
4
8
7
6
5
V
CS  
SO  
WP  
1
2
3
4
8
7
6
5
V
CC  
HOLD  
SCK  
CC  
CS  
SO  
WP  
HOLD  
SCK  
SI  
V
SI  
SS  
V
SS  
COLUMN  
DECODERS  
WORD ADDRESS  
BUFFERS  
DIP Package (P, L, GL)  
TSSOP Package (U, Y, GY)  
1
2
3
4
8
7
6
5
V
CS  
SO  
CC  
1
2
3
4
8
7
6
5
SO  
SI  
CS  
I/O  
CONTROL  
V
CC  
HOLD  
SCK  
SI  
SO  
HOLD  
SCK  
SI  
WP  
WP  
V
SS  
E2PROM  
ARRAY  
CS  
V
SPI  
CONTROL  
LOGIC  
XDEC  
SS  
WP  
HOLD  
SCK  
PIN FUNCTIONS  
Pin Name  
SO  
Function  
BLOCK  
PROTECT  
LOGIC  
Serial Data Output  
Serial Clock  
DATA IN  
STORAGE  
SCK  
WP  
Write Protect  
HIGH VOLTAGE/  
TIMING CONTROL  
VCC  
+1.8V to +5.5V Power Supply  
Ground  
STATUS  
REGISTER  
VSS  
CS  
Chip Select  
SI  
Serial Data Input  
Suspends Serial Input  
No Connect  
HOLD  
NC  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1006, Rev. M  
1
1234567...11

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