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CAT24WC02PE-1.8REV-E PDF预览

CAT24WC02PE-1.8REV-E

更新时间: 2024-11-26 17:04:31
品牌 Logo 应用领域
安森美 - ONSEMI 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
14页 2253K
描述
IC,SERIAL EEPROM,256X8,CMOS,DIP,8PIN,PLASTIC

CAT24WC02PE-1.8REV-E 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.91
数据保留时间-最小值:100耐久性:1000000 Write/Erase Cycles
I2C控制字节:1010DDDRJESD-30 代码:R-PDIP-T8
内存密度:2048 bit内存集成电路类型:EEPROM
内存宽度:8端子数量:8
字数:256 words字数代码:256
最高工作温度:125 °C最低工作温度:-40 °C
组织:256X8封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP8,.3
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:SERIAL电源:2/5 V
认证状态:Not Qualified串行总线类型:I2C
最大待机电流:0.000001 A子类别:EEPROMs
最大压摆率:0.003 mA表面贴装:NO
技术:CMOS温度等级:AUTOMOTIVE
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL写保护:HARDWARE
Base Number Matches:1

CAT24WC02PE-1.8REV-E 数据手册

 浏览型号CAT24WC02PE-1.8REV-E的Datasheet PDF文件第2页浏览型号CAT24WC02PE-1.8REV-E的Datasheet PDF文件第3页浏览型号CAT24WC02PE-1.8REV-E的Datasheet PDF文件第4页浏览型号CAT24WC02PE-1.8REV-E的Datasheet PDF文件第5页浏览型号CAT24WC02PE-1.8REV-E的Datasheet PDF文件第6页浏览型号CAT24WC02PE-1.8REV-E的Datasheet PDF文件第7页 
CAT24WC01/02/04/08/16  
1K/2K/4K/8K/16K-Bit Serial EEPROM  
FEATURES  
Self-Timed Write Cycle with Auto-Clear  
1,000,000 Program/Erase Cycles  
100 Year Data Retention  
400 kHz I2C Bus Compatible*  
1.8 to 5.5Volt Operation  
Low Power CMOS Technology  
8-pin DIP, SOIC, TSSOP and MSOP packages  
- "Green" package option available  
Write Protect Feature  
— Entire Array Protected When WP at VIH  
Commercial, Industrial, Automotive and  
Page Write Buffer  
Extended Temperature Ranges  
DESCRIPTION  
08/16 feature a 16-byte page write buffer. The device  
operates via the I2C bus serial interface, has a special  
write protection feature, and is available in 8-pin DIP,  
SOIC, TSSOP and MSOP packages.  
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K-  
bit Serial CMOS EEPROM internally organized as 128/  
256/512/1024/2048 words of 8 bits each. Catalyst’s  
advanced CMOS technology substantially reduces de-  
vice power requirements. The the CAT24WC01/02/04/  
PIN CONFIGURATION  
DIP Package (P, L, GL)  
BLOCK DIAGRAM  
SOIC Package (J, W, GW)  
EXTERNAL LOAD  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A
A
A
V
A
A
A
0
1
2
CC  
0
1
2
V
CC  
WP  
SENSE AMPS  
SHIFT REGISTERS  
D
OUT  
WP  
ACK  
SCL  
SDA  
SCL  
SDA  
V
V
V
SS  
CC  
SS  
WORD ADDRESS  
BUFFERS  
COLUMN  
DECODERS  
V
SS  
5020 FHD F01  
TSSOP Package (U, Y, GY)  
START/STOP  
(MSOP and TSSOP available for CAT24WC01,  
CAT24WC02 and CAT24WC04 only)  
MSOP Package (R, Z, GZ)  
SDA  
WP  
LOGIC  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
A0  
A1  
A2  
A
A
A
CC  
0
1
2
V
CC  
WP  
WP  
E2PROM  
XDEC  
SCL  
SDA  
SCL  
SDA  
CONTROL  
LOGIC  
V
V
SS  
SS  
PIN FUNCTIONS  
DATA IN STORAGE  
Pin Name  
Function  
A0, A1, A2  
SDA  
Device Address Inputs  
Serial Data/Address  
Serial Clock  
HIGH VOLTAGE/  
TIMING CONTROL  
SCL  
SCL  
STATE COUNTERS  
WP  
Write Protect  
SLAVE  
ADDRESS  
COMPARATORS  
A
0
A1  
A2  
VCC  
+1.8V to +5.5V Power Supply  
Ground  
VSS  
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
1

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