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CAT24C208UE-TE13 PDF预览

CAT24C208UE-TE13

更新时间: 2024-11-26 21:00:19
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
16页 116K
描述
EEPROM, 1KX8, Serial, CMOS, PDSO8, MO-153AA, TSSOP-8

CAT24C208UE-TE13 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP,针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.34
最大时钟频率 (fCLK):0.4 MHzJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.4 mm
内存密度:8192 bit内存集成电路类型:EEPROM
内存宽度:8湿度敏感等级:1
功能数量:1端子数量:8
字数:1024 words字数代码:1000
工作模式:SYNCHRONOUS最高工作温度:125 °C
最低工作温度:-40 °C组织:1KX8
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:SERIAL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.2 mm
串行总线类型:I2C最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3 mm最长写入周期时间 (tWC):5 ms
Base Number Matches:1

CAT24C208UE-TE13 数据手册

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Advance Information  
E
CAT24C208  
8K (1K x 8) -Bit Dual Port Serial EEPROM for VESA Plug and Play Applications  
in LCD Projectors and Monitors  
TM  
FEATURES  
400 kHz I2C bus compatible*  
1,000,000 program/erase cycles  
100 year data retention  
Complies with VESA E-EDID, E-DDC, DI-EXT  
and M1 specifications  
8-pin DIP, SOIC, TSSOP or MSOP packages  
- Green package option  
3V to 5.5V volt operation  
Industrial and extended temperature ranges  
Low power CMOS technology  
16-byte page write buffer  
Self-timed write cycle with auto-clear  
DESCRIPTION  
Using Catalyst's advanced CMOS technology which  
substantially reduces device power requirements, the  
CAT24C208 can be powered from either of two  
independent VCC inputs.  
The CAT24C208 is an 8k-bit Dual Port Serial CMOS  
EEPROM internally organized as 1k words of 8 bits  
each. The CAT24C208 features a 16-byte page write  
buffer and can be accessed from either of two separate  
I2C compatible ports, DSP (SDA, SCL) and DDC (SDA,  
SCL) which conform to the VESA E-EDID EEPROM  
Standard.  
The CAT24C208 operates over the full industrial and  
extended temperature range and is available in  
miniature 8-pin DIP, SOIC, TSSOP and MSOP  
packages.  
Arbitration between the two interface ports is automatic  
and allows the appearance of individual access to the  
memory from each interface.  
BLOCK DIAGRAM  
DSP V  
CC  
DDC V  
CC  
ARBITRATION  
LOGIC  
D
E
C
O
D
E
R
S
D
E
C
O
D
E
R
S
1K X 8  
MEMORY  
ARRAY  
DDC  
CONTROL  
LOGIC  
DISPLAY  
CONTROL  
LOGIC  
DSP SCL  
DSP SDA  
DDC SCL  
DDC SDA  
CONFIGURATION  
REGISTER  
EDID SEL  
V
SS  
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1044, Rev. D  
1

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