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CAT24AC128YI-1.8TE13REVA PDF预览

CAT24AC128YI-1.8TE13REVA

更新时间: 2024-10-28 13:06:35
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
11页 666K
描述
EEPROM, 16KX8, Serial, CMOS, PDSO14, LEAD AND HALOGEN FREE, TSSOP-14

CAT24AC128YI-1.8TE13REVA 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP,
针数:14Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.84Is Samacsys:N
最大时钟频率 (fCLK):0.1 MHzJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:5 mm
内存密度:131072 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:14字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:16KX8封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行:SERIAL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.1 mm串行总线类型:I2C
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
最长写入周期时间 (tWC):5 msBase Number Matches:1

CAT24AC128YI-1.8TE13REVA 数据手册

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Not Recommended for New Design,  
Replace with CAT24C128  
E
CAT24AC128  
128kbit I2C Serial CMOS EEPROM With Three Chip Address Input Pins  
E TM  
R
FEATURES  
I 400kHz (2.5V) and 100kHz (1.8V) I2C bus  
I Commercial, industrial and extended  
compatibility  
automotive temperature ranges  
I 1.8 to 5.5 volt operation  
I Low power CMOS technology  
I Write protect feature  
– Entire array protected when WP at VIH  
I 1,000,000 program/erase cycles  
I 100 year data retention  
I Schmitt trigger filtered inputs for noise  
suppression  
I 64-Byte page write buffer  
I 8-Pin DIP, 8-Pin SOIC (JEDEC/EIAJ) or  
14-pin TSSOP  
I Self-timed write cycle with auto-clear  
DESCRIPTION  
The CAT24AC128 is a 128kbit Serial CMOS EEPROM  
internally organized as 16,384 words of 8 bits each.  
Catalyst’s advanced CMOS technology substantially  
reducesdevicepowerrequirements. TheCAT24AC128  
featuresa64-bytepagewritebuffer.Thedeviceoperates  
via the I2C bus serial interface and is available in 8-pin  
DIP, 8-pin SOIC or 14-pin TSSOP packages. Three  
device address inputs allows up to 8 devices to share a  
common 2-wire I2C bus.  
BLOCK DIAGRAM  
PIN CONFIGURATION  
DIP Package (P, L)  
SOIC Package (J, K, W, X)  
EXTERNAL LOAD  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
CC  
WP  
A0  
A1  
A2  
A0  
A1  
CC  
SENSE AMPS  
SHIFT REGISTERS  
D
OUT  
WP  
ACK  
A2  
SCL  
SDA  
SCL  
SDA  
V
V
CC  
SS  
V
V
SS  
SS  
WORD ADDRESS  
BUFFERS  
COLUMN  
DECODERS  
TSSOP Package (U14, Y14)  
512  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
A0  
V
WP  
NC  
NC  
NC  
CC  
START/STOP  
SDA  
A1  
NC  
NC  
NC  
A2  
LOGIC  
E2PROM  
256X512  
XDEC  
256  
SCL  
SDA  
V
8
SS  
CONTROL  
LOGIC  
WP  
PIN FUNCTIONS  
DATA IN STORAGE  
Pin Name  
Function  
SDA  
SCL  
WP  
Serial Data/Address  
Serial Clock  
HIGH VOLTAGE/  
TIMING CONTROL  
Write Protect  
SCL  
STATE COUNTERS  
VCC  
+1.8V to +5.5V Power Supply  
Ground  
SLAVE  
ADDRESS  
COMPARATORS  
A0  
A1  
A2  
VSS  
A0 - A2  
Device Address Inputs  
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.  
© Catalyst Semiconductor, Inc.  
Doc. No. 1028, Rev. J  
1
Characteristics subject to change without notice  

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