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CAT24AC128JI-TE13 PDF预览

CAT24AC128JI-TE13

更新时间: 2024-10-27 22:24:47
品牌 Logo 应用领域
CATALYST 存储内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
11页 475K
描述
128kbit I2C Serial CMOS EEPROM With Three Chip Address Input Pins

CAT24AC128JI-TE13 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.92Is Samacsys:N
最大时钟频率 (fCLK):0.4 MHz数据保留时间-最小值:100
耐久性:1000000 Write/Erase CyclesI2C控制字节:1010DDDR
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm内存密度:131072 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:8
字数:16384 words字数代码:16000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:16KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):240电源:3/5 V
认证状态:Not Qualified座面最大高度:1.75 mm
串行总线类型:I2C最大待机电流:0.000001 A
子类别:EEPROMs最大压摆率:0.003 mA
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2.5 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
最长写入周期时间 (tWC):5 ms写保护:HARDWARE
Base Number Matches:1

CAT24AC128JI-TE13 数据手册

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E
CAT24AC128  
128kbit I2C Serial CMOS EEPROM With Three Chip Address Input Pins  
E TM  
R
FEATURES  
I 400kHz (2.5V) and 100kHz (1.8V) I2C bus  
I Commercial, industrial and extended  
compatibility  
automotive temperature ranges  
I 1.8 to 5.5 volt operation  
I Low power CMOS technology  
I Write protect feature  
– Entire array protected when WP at VIH  
I 1,000,000 program/erase cycles  
I 100 year data retention  
I Schmitt trigger filtered inputs for noise  
suppression  
I 64-Byte page write buffer  
I 8-Pin DIP, 8-Pin SOIC (JEDEC/EIAJ) or  
14-pin TSSOP  
I Self-timed write cycle with auto-clear  
DESCRIPTION  
The CAT24AC128 is a 128kbit Serial CMOS EEPROM  
internally organized as 16,384 words of 8 bits each.  
Catalyst’s advanced CMOS technology substantially  
reducesdevicepowerrequirements. TheCAT24AC128  
featuresa64-bytepagewritebuffer.Thedeviceoperates  
via the I2C bus serial interface and is available in 8-pin  
DIP, 8-pin SOIC or 14-pin TSSOP packages. Three  
device address inputs allows up to 8 devices to share a  
common 2-wire I2C bus.  
BLOCK DIAGRAM  
PIN CONFIGURATION  
DIP Package (P, L)  
SOIC Package (J, K, W, X)  
EXTERNAL LOAD  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
CC  
WP  
A0  
A1  
A2  
A0  
A1  
CC  
SENSE AMPS  
SHIFT REGISTERS  
D
OUT  
WP  
ACK  
A2  
SCL  
SDA  
SCL  
SDA  
V
V
CC  
SS  
V
V
SS  
SS  
WORD ADDRESS  
BUFFERS  
COLUMN  
DECODERS  
TSSOP Package (U14, Y14)  
512  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
A0  
V
WP  
NC  
NC  
NC  
CC  
START/STOP  
SDA  
A1  
NC  
NC  
NC  
A2  
LOGIC  
E2PROM  
256X512  
XDEC  
256  
SCL  
SDA  
V
8
SS  
CONTROL  
LOGIC  
WP  
PIN FUNCTIONS  
DATA IN STORAGE  
Pin Name  
Function  
SDA  
SCL  
WP  
Serial Data/Address  
Serial Clock  
HIGH VOLTAGE/  
TIMING CONTROL  
Write Protect  
SCL  
STATE COUNTERS  
VCC  
+1.8V to +5.5V Power Supply  
Ground  
SLAVE  
ADDRESS  
COMPARATORS  
A0  
A1  
A2  
VSS  
A0 - A2  
Device Address Inputs  
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.  
© 2004 by Catalyst Semiconductor, Inc.  
Doc. No. 1028, Rev. I  
1
Characteristics subject to change without notice  

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