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CAT1163J-28TE13 PDF预览

CAT1163J-28TE13

更新时间： 2024-11-26 19:57:23
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管外围集成电路
页数 文件大小 规格书
12页 140K
描述
SPECIALTY MICROPROCESSOR CIRCUIT, PDSO8, SOIC-8

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中文翻译

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CAT1163J-28TE13 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：8
Reach Compliance Code：compliantHTS代码：8542.31.00.01
风险等级：5.66JESD-30 代码：R-PDSO-G8
JESD-609代码：e0长度：4.9 mm
端子数量：8最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：240
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压：6 V最小供电电压：2.7 V
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3.9 mm
uPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUITBase Number Matches：1

CAT1163J-28TE13 数据手册

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CAT1163  
Supervisory Circuits with  
I2C Serial CMOS EEPROM,  
Precision Reset Controller  
and Watchdog Timer (16K)  
http://onsemi.com  
Description  
The CAT1163 is a complete memory and supervisory solution for  
microcontroller−based systems. A serial EEPROM memory (16K)  
with hardware memory write protection, a system power supervisor  
with brown out protection and a watchdog timer are integrated  
together in low power CMOS technology. Memory interface is via an  
PDIP−8  
CASE 646AA  
SOIC−8  
CASE 751BD  
2
I C bus.  
The 1.6−second watchdog circuit returns a system to a known good  
state if a software or hardware glitch halts or “hangs” the system. The  
CAT1163 watchdog monitors the WDI input pin.  
PIN CONFIGURATION  
The power supply monitor and reset circuit protects memory and  
system controllers during power up/down and against brownout  
conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V  
systems. If power supply voltages are out of tolerance reset signals  
become active, preventing the system microcontroller, ASIC or  
peripherals from operating. Reset signals become inactive typically  
200 ms after the supply voltage exceeds the reset threshold level. With  
both active high and low reset signals, interface to microcontrollers  
and other ICs is simple. In addition, a reset pin can be used as a  
debounced input for pushbutton manual reset capability.  
PDIP 8 Lead  
SOIC 8 Lead  
WDI  
1
2
3
4
8
7
6
5
V
CC  
RESET  
RESET  
CAT1163  
WP  
SCL  
SDA  
GND  
PIN FUNCTIONS  
Function  
The CAT1163 memory features a 16−byte page. In addition,  
hardware data protection is provided by a write protect pin WP and by  
Pin Name  
WDI  
RESET  
WP  
Watchdog Timer Input  
Active Low Reset I/O  
Write Protect  
a V sense circuit that prevents writes to memory whenever V falls  
CC  
CC  
below the reset threshold or until V reaches the reset threshold  
CC  
during power up.  
Available packages include an 8−pin DIP and a surface mount,  
8−pin SO package.  
GND  
Ground  
SDA  
Serial Data/Address  
Clock Input  
SCL  
Features  
RESET  
Active High Reset I/O  
Power Supply  
• Watchdog Timer Input (WDI)  
2
V
CC  
• 400 kHz I C Bus Compatible  
• 2.7 V to 6.0 V Operation  
• Low Power CMOS Technology  
• 16−Byte Page Write Buffer  
ORDERING INFORMATION  
For Ordering Information details, see page 10.  
• Built−in Inadvertent Write Protection  
♦ V Lock Out  
CC  
♦ Write Protection Pin, WP  
• 100 Year Data Retention  
• Active High or Low Reset  
♦ Precision Power Supply Voltage Monitor  
♦ 5 V, 3.3 V and 3 V Systems  
• 8−Pin DIP or 8−Pin SOIC  
• Commercial and Industrial Temperature Ranges  
♦ Five Threshold Voltage Options  
• These Devices are Pb−Free, Halogen Free/BFR Free  
• 1,000,000 Program/Erase Cycles  
• Manual Reset  
and are RoHS Compliant  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
November, 2011 − Rev. 10  
CAT1163/D  
1234567...12

中文翻译

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