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CAHCT240IPWRG4Q1 PDF预览

CAHCT240IPWRG4Q1

更新时间: 2024-11-18 12:50:47
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
9页 178K
描述
OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS

CAHCT240IPWRG4Q1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.77
控制类型:ENABLE LOW计数方向:UNIDIRECTIONAL
系列:AHCT/VHCT/VTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):260最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:9.5 ns传播延迟(tpd):9.5 ns
认证状态:Not Qualified筛选级别:AEC-Q100
座面最大高度:1.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:4.4 mm
Base Number Matches:1

CAHCT240IPWRG4Q1 数据手册

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ꢍ ꢆꢇꢄꢎ ꢏꢐꢑ ꢑ ꢒ ꢓꢔ ꢕꢓ ꢖ ꢗꢒ ꢓ  
ꢘ ꢖꢇ ꢅ ꢙ ꢊꢀꢇꢄꢇ ꢒ ꢍ ꢐꢇ ꢚꢐ ꢇꢀ  
SCLS582B − APRIL 2004 − REVISED APRIL 2008  
PW PACKAGE  
(TOP VIEW)  
D
D
D
Qualified for Automotive Applications  
Inputs Are TTL-Voltage Compatible  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
2A2  
1Y4  
2A1  
description/ordering information  
This octal buffer/driver is designed specifically to  
improve the performance and density of 3-state  
memory-address drivers, clock drivers, and  
bus-oriented receivers and transmitters.  
The SN74AHCT240 device is organized as two 4-bit  
buffers/line drivers with separate output-enable (OE)  
inputs. When OE is low, the device passes data from  
the A inputs to the Y outputs. When OE is high, the  
outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE shall be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
{
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
−40°C to 85°C  
TSSOP − PW Tape and reel  
SN74AHCT240IPWRQ1  
AHCT240I  
For the most current package and ordering information, see the Package Option Addendum at the end of this  
document, or see the TI web site at http://www.ti.com.  
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.  
FUNCTION TABLE  
(each 4-bit buffer/driver)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
L
H
Z
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢇꢦ  
Copyright 2008, Texas Instruments Incorporated  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

CAHCT240IPWRG4Q1 替代型号

型号 品牌 替代类型 描述 数据表
SN74HCT240PWE4 TI

完全替代

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SN74HCT240PWR TI

类似代替

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SN74HCT240PW TI

类似代替

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

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