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CAHCT125QPWRG4Q1 PDF预览

CAHCT125QPWRG4Q1

更新时间: 2024-11-24 12:50:47
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
11页 250K
描述
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

CAHCT125QPWRG4Q1 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:GREEN, PLASTIC, TSSOP-14针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:8 weeks
风险等级:0.89Is Samacsys:N
控制类型:ENABLE LOW计数方向:UNIDIRECTIONAL
系列:AHCT/VHCT/VTJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:4功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):0.02 mAProp。Delay @ Nom-Sup:8.5 ns
传播延迟(tpd):8.5 ns认证状态:Not Qualified
筛选级别:AEC-Q100座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:4.4 mm
Base Number Matches:1

CAHCT125QPWRG4Q1 数据手册

 浏览型号CAHCT125QPWRG4Q1的Datasheet PDF文件第2页浏览型号CAHCT125QPWRG4Q1的Datasheet PDF文件第3页浏览型号CAHCT125QPWRG4Q1的Datasheet PDF文件第4页浏览型号CAHCT125QPWRG4Q1的Datasheet PDF文件第5页浏览型号CAHCT125QPWRG4Q1的Datasheet PDF文件第6页浏览型号CAHCT125QPWRG4Q1的Datasheet PDF文件第7页 
SN74AHCT125-Q1  
QUADRUPLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
SCLS508A − JUNE 2003 − REVISED FEBRUARY 2008  
D OR PW PACKAGE  
(TOP VIEW)  
D
D
Qualified for Automotive Applications  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1OE  
1A  
VCC  
4OE  
4A  
1
2
3
4
5
6
7
14  
13  
12  
D
Inputs Are TTL-Voltage Compatible  
1Y  
2OE  
2A  
2Y  
11 4Y  
description/ordering information  
10  
9
3OE  
3A  
The SN74AHCT125 is a quadruple bus buffer gate  
featuring independent line drivers with 3-state  
outputs. Each output is disabled when the associated  
output-enable (OE) input is high. When OE is low, the  
respective gate passes the data from the A input to  
its Y output.  
8
GND  
3Y  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
SOIC − D  
Tape and reel  
Tape and reel  
SN74AHCT125QDRQ1  
AHCT125Q  
−40°C to 125°C  
TSSOP − PW  
SN74AHCT125QPWRQ1 HB125Q  
For the most current package and ordering information, see the Package Option Addendum at the end of this  
document, or see the TI web site at http://www.ti.com.  
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright © 2008, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

CAHCT125QPWRG4Q1 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHCT125QPWRQ1 TI

完全替代

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74AHCT125PWR TI

完全替代

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHCT125PWE4 TI

完全替代

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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