CA555, CA555C,
S E M I C O N D U C T O R
LM555, LM555C, NE555
Timers for Timing Delays and Oscillator Application
in Commercial, Industrial and Military Equipment
May 1997
Features
Description
• Accurate Timing From Microseconds Through Hours
• Astable and Monostable Operation
• Adjustable Duty Cycle
The CA555 and CA555C are highly stable timers for use in
precision timing and oscillator applications. As timers, these
monolithic integrated circuits are capable of producing accu-
rate time delays for periods ranging from microseconds
through hours. These devices are also useful for astable
oscillator operation and can maintain an accurately con-
trolled free running frequency and duty cycle with only two
external resistors and one capacitor.
• Output Capable of Sourcing or Sinking up to 200mA
• Output Capable of Driving TTL Devices
• Normally ON and OFF Outputs
o
• High Temperature Stability . . . . . . . . . . . . . . 0.005%/ C
• Directly Interchangeable with SE555, NE555, MC1555,
and MC1455
Applications
• Precision Timing
• Sequential Timing
• Time Delay Generation
The circuits of the CA555 and CA555C may be triggered by
the falling edge of the waveform signal, and the output of
these circuits can source or sink up to a 200mA current or
drive TTL circuits.
• Pulse Generation
• Pulse Detector
• Pulse Width and Position
Modulation
These types are direct replacements for industry types in
packages with similar terminal arrangements e.g. SE555
and NE555, MC1555 and MC1455, respectively. The CA555
type circuits are intended for applications requiring premium
electrical performance. The CA555C type circuits are
intended for applications requiring less stringent electrical
characteristics.
Ordering Information
PART NUMBER
TEMP.
PKG.
NO.
o
(BRAND)
RANGE ( C)
PACKAGE
CA0555E
-55 to 125 8 Ld PDIP
-55 to 125 8 Ld SOIC
-55 to 125 8 Ld SOIC †
-55 to 125 8 Pin Metal Can
E8.3
CA0555M (555)
CA0555M96 (555)
CA0555T
M8.15
M8.15
T8.C
E8.3
CA0555CE
0 to 70
0 to 70
0 to 70
0 to 70
8 Ld PDIP
CA0555CM (555C)
CA0555CM96 (555C)
CA0555CT
8 Ld SOIC
M8.15
M8.15
T8.C
E8.3
8 Ld SOIC †
8 Pin Metal Can
LM555N
-55 to 125 8 Ld PDIP
LM555CN
0 to 70
0 to 70
8 Ld PDIP
8 Ld PDIP
E8.3
NE555N
E8.3
NOTE: † Denotes Tape and Reel
Pinouts
Functional Block Diagram
CA555, CA555C (PDIP, SOIC)
LM555, LM555C, NE555 (PDIP)
TOP VIEW
V+
8
TRIGGER
CONTROL
VOLTAGE
5
2
1
2
3
4
8
7
6
5
GND
TRIGGER
OUTPUT
RESET
V+
DISCHARGE
THRESHOLD
TRIGGER
COMPAR
3
7
CONTROL
VOLTAGE
6
4
OUTPUT
THRESHOLD
COMPAR
CA555, CA555C (METAL CAN)
TOP VIEW
V+
8
TAB
FLIP-FLOP
GND
1
3
7
5
DISCHARGE
6 THRESHOLD
2
TRIGGER
1
GND
CONTROL
VOLTAGE
OUTPUT
4
RESET
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 834.4
Copyright © Harris Corporation 1997
8-3