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CA3242

更新时间： 2024-11-10 22:40:07
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英特矽尔 - INTERSIL 驱动器栅
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1页 17K
描述
Quad-Gated Inverting Power Driver For Interfacing Low-Level Logic to High Current Load

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CA3242 数据手册

  
CA3242  
Quad-Gated Inverting Power Driver For  
Interfacing Low-Level Logic to High Current Load  
August 1998  
Features  
Description  
• Driven Outputs Capable of Switching 600mA Load The CA3242 quad-gated inverting power driver contains four  
Currents Without Spurious Changes in Output State  
• Inputs Compatible with TTL or 5V CMOS Logic  
• Suitable for Resistive or Inductive Loads  
• Output Overload Protection  
gate switches for interfacing low-level logic to inductive and  
resistive loads such as: relays, solenoids, AC and DC  
motors, heaters, incandescent displays, and vacuum fluo-  
rescent displays.  
Output overload protection is provided when the load current  
(approximately 1.2A) causes the output VCE(sat) to rise  
above 1.3V. A built-in time delay, nominally 25µs, is provided  
during output turn-on as output drops from VDD to VSAT. That  
output will be shut down by its protection network without  
affecting the other outputs. The corresponding Input or  
Enable must be toggled to reset the output protection circuit.  
• Power-Frame Construction for Good Heat Dissipation  
Applications  
• Relays  
• Solenoids  
Steering diodes in the outputs in conjunction with external  
zener diodes protect the IC against voltage transients due to  
switching inductive loads.  
• AC and DC Motors  
• Heaters  
To allow for maximum heat transfer from the chip, the four  
center leads are directly connected to the die mounting pad.  
In free air, junction-to-air thermal resistance (RθJA) is 60oC/W  
(typical). This coefficient can be lowered by suitable design  
of the PC board to which the CA3242 is soldered.  
• Incandescent Displays  
• Vacuum Fluorescent Displays  
Ordering Information  
TEMPERATURE  
PART NUMBER  
RANGE  
PACKAGE  
o
o
CA3242E  
-40 C to +105 C  
16 Lead Plastic DIP  
Pinout  
Block Diagram  
CA3242 (PDIP)  
TOP VIEW  
8
OUT D  
CLAMP  
OUT C  
P
P
9
IN D  
IN C  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
7
6
OUT A  
CLAMP  
OUT B  
GND  
IN A  
10  
IN B  
TRUTH TABLE  
ENABLE  
GND  
ENABLE  
IN  
H
L
OUT  
L
11  
VCC  
GND  
H
H
L
GND  
GND 12  
GND  
5
4
3
GND  
GND  
OUT C  
CLAMP  
OUT D  
VCC  
INC  
IND  
H
13  
ENABLE 14  
X
H
P
P
OUT B  
CLAMP  
2
1
15  
16  
IN B  
IN A  
OUT A  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 1561.2  
407-727-9207 | Copyright © Intersil Corporation 1999  
2-3  
1

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