Datasheet > C9820BYB

C9820BYB

更新时间： 2024-01-19 05:04:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟光电二极管外围集成电路晶体
页数	文件大小	规格书
17页	147K
描述
Processor Specific Clock Generator, CMOS, PDSO24, 0.150 INCH, SSOP-24

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技术参数
数据手册

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C9820BYB 技术参数

生命周期：	Transferred	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	24
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.27
JESD-30 代码：	R-PDSO-G24	长度：	8.65 mm
端子数量：	24	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	主时钟/晶体标称频率：	67 MHz
认证状态：	Not Qualified	座面最大高度：	1.75 mm
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	宽度：	3.9 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

C9820BYB 数据手册

C9820

Direct Rambus Clock Generator

Preliminary

Product Features

Product Description

•

High Speed Clock support - provides a 400MHz

differential clock source for Direct Rambus

memory systems for an 800MHz data transfer

rate

Synchronization Flexibility - provides signals to

synchronize the clock domains of the Rambus

Channel with an external system or processor

clock, provided by C9801 and C9812.

Power Management Support permits channel

clocks to be enabled and disabled as required

Supports Independent Channel Clocking

24 pin 150 mil SSOP Package

The C9820 is a Rambus compliant DRCG clock

synchronizer. It contains a Phase Locked Loop that

provides complimentary Rambus memory clocks.

Included in its functionality is the control logic to

phase and frequency synchronizing the device’s

output clocks with the system reference clock. Power

management logic is also provided for Mobil

application and green PC functionality. Also included

are separate power pins for each internal functional

block so as to minimize interaction of these sections

with each other and thus maximize the device

performance.

•

Supports Intel Architecture platforms

Pin Configuration

Block Diagram

VddlR

Refclk

VddP

REFCLK

PLL

MULT 0:1

VddO

VssO

Clk

VssP

Output

Control

Logic

VssI

CLK

CLKB

Phase

Aligner

PCLKM

PclkM

SynClkN

VssC

N/C

SYNCLKN

ClkB

VssO

VddO

Mult0

Mult1

VddC

VddlPD

StopB

PwrDnB

Test

Logic

S0:2

STOPB

Figure: 2

Figure: 1

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.

MILPITAS, CA, Tel: 408-263-6300, Fax: 408-263-6571

http://www.imicorp.com

Rev 1.3

9/7/1999

Page 1 of 17

12 3 4 5 6 7...17

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