C8051F016
25 MIPS, 32 kB Flash, 10-Bit ADC, 48-Pin Mixed-Signal MCU
Analog Peripherals
High-Speed 8051 µC Core
10-Bit ADC
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Pipelined instruction architecture; executes 70% of Instructions in 1 or 2
system clocks
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±1 LSB INL; no missing codes
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Up to 25 MIPS throughput with 25 MHz clock
Programmable throughput up to 100 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
Expanded interrupt handler; up to 21 interrupt sources
Memory
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2304 bytes data RAM
32 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
Two 12-Bit DACs
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Voltage output
Digital Peripherals
10 µsec settling time
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16 port I/O; all are 5 V tolerant
Two Comparators
Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports
available concurrently
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16 programmable hysteresis values
Configurable to generate interrupts or reset
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Programmable 16-bit counter/timer array with five capture/compare
modules
Internal Voltage Reference
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4 general-purpose 16-bit counter/timers
V
Monitor/Brown-out Detector
DD
Dedicated watchdog timer; bidirectional reset
On-Chip JTAG Debug
Clock Sources
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On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Fully compliant with IEEE 1149.1 specification
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Internal programmable oscillator: 2–16 MHz
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
Package
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48-pin TQFP (standard lead and lead-free packages)
Ordering Part Numbers
Supply Voltage: 2.7 to 3.6 V
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Lead-free package: C8051F016-GQ
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Typical operating current: 12.5 mA at 25 MHz
Standard package: C8051F016
Multiple power saving sleep and shutdown modes
- Temperature Range: –40 to +85 °C
VDD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
VDD
Digital Power
P
0
DGND
DGND
DGND
DGND
UART
C
R
O
S
S
B
A
R
SMBus
D
r
v
SPI Bus
AV+
AV+
AGND
AGND
Analog Power
5-Chnl
PCA
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P
1
Timers
0,1,2
32 kB
FLASH
TCK
TMS
TDI
Boundary Scan
8
0
5
1
JTAG
Logic
D
r
v
Debug HW
TDO
Timer 3
256 Byte
RAM
Reset
S
W
I
T
C
H
RST
Port 0
Latch
P
2
VDD
Monitor
2048 Byte
XRAM
WDT
Port 1
Latch
D
r
v
External
Oscillator
Circuit
C
o
r
XTAL1
XTAL2
Port 2
Latch
System Clock
SFR Bus
Internal
Oscillator
P
3
Port 3
Latch
e
VREF
DAC1
VREF
D
r
v
DAC1
(12-Bit)
DAC0
(12-Bit)
DAC0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
ADC
100 ksps
(10-Bit)
A
M
U
X
Prog
Gain
TEMP
SENSOR
CP0+
CP0-
CP1+
CP1-
CP0
CP1
Precision Mixed Signal
Copyright © 2005 by Silicon Laboratories
5.5.2005