Datasheet > C3K-L67140V-55

C3K-L67140V-55

更新时间： 2024-10-29 06:40:19

品牌	Logo	应用领域
TEMIC		静态存储器光电二极管
页数	文件大小	规格书
16页	196K
描述
Dual-Port SRAM, 1KX8, 55ns, CMOS, PDIP48, 0.600 INCH, PLASTIC, DIP-48

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C3K-L67140V-55 数据手册

L67130/L67140

1 K × 8 CMOS Dual Port RAM 3.3 Volt

Introduction

The L67130/67140 are very low power CMOS dual port Using an array of eight transistors (8T) memory cell and

static RAMs organized as 1024 × 8. They are designed to fabricated with the state of the art 1.0 µm lithography

be used as a stand-alone 8 bits dual port RAM or as a named SCMOS, the M67130/140 combine an extremely

combination MASTER/SLAVE dual port for 16 bits or low standby supply current (typ = 1.0 µA) with a fast

more width systems. The MHS MASTER/SLAVE dual access time at 45 ns over the full temperature range. All

port approach in memory system applications results in versions offer battery backup data retention capability

full speed, error free operation without the need for with a typical power consumption at less than 5 µW.

additional discrete logic.

For military/space applications that demand superior

Master and slave devices provide two independent ports

with separate control, address and I/O pins that permit

independent, asynchronous access for reads and writes to

any location in the memory. An automatic power down

feature controlled by CS permits the onchip circuitry of

each port in order to enter a very low stand by power

mode.

levels of performance and reliability the L67130/67140

is processed according to the methods of the latest

revision of the MIL STD 883 (class B or S) and/or ESA

SCC 9000.

Features

D Single 3.3 V ± 0.3 volt power supply

D Fast access time

D On chip arbitration logic

D BUSY output flag on master

45 ns(*) to 70 ns

D BUSY input flag on slave

D 67130L/67140L low power

D INT flag for port to port communication

D Fully asynchronous operation from either port

D Battery backup operation : 2 V data retention

67130V/67140V very low power

D Expandable data bus to 16 bits or more using master/slave

devices when using more than one device.

(*) Preliminary

MATRA MHS

Rev. D (19 Fev. 97)

12 3 4 5 6 7...16

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