BUK566-60A

更新时间： 2024-11-25 22:17:31

品牌	Logo	应用领域
恩智浦 - NXP		晶体晶体管
页数	文件大小	规格书
7页	59K
描述
PowerMOS transistor Logic level FET

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中文翻译

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BUK566-60A 数据手册

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level FET

BUK566-60A

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode

logic level field-effect power

transistor in a plastic envelope

suitable for surface mount

SYMBOL

PARAMETER

MAX.

UNIT

V_DS

I_D

Drain-source voltage

Drain current (DC)

Total power dissipation

Drain-source on-state resistance

150

applications.

P_tot

The device is intended for use in

Switched Mode Power Supplies

(SMPS), motor control, welding,

DC/DC and AC/DC converters, and

in automotive and general purpose

switching applications.

R_DS(ON)

mΩ

V_GS= 5 V

PINNING - SOT404

PIN CONFIGURATION

SYMBOL

DESCRIPTION

gate

drain

source

mb drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DS

V_DGR

±V_GS

±V_GSM

I_D

Drain-source voltage

Drain-gate voltage

R_GS= 20 kΩ

Gate-source voltage

Non-repetitive gate-source voltage

Drain current (DC)

t_p≤ 50 µs

T_mb= 25 ˚C

T_mb= 100 ˚C

T_mb= 25 ˚C

I_D

I_DM

Drain current (pulse peak value)

Total power dissipation

Storage temperature

200

150

175

P_tot

T_stg

T_j

- 55

˚C

Junction temperature

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

R_{th j-mb}

Thermal resistance junction to

mounting base

Thermal resistance junction to minimum footprint,

ambient FR4 boards (see. Fig 18).

1.0

K/W

R_{th j-a}

K/W

February 1996

Rev 1.000

12 3 4 5 6 7

中文翻译

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