Datasheet > BUK562-100A

BUK562-100A

更新时间： 2024-11-25 22:50:23

品牌	Logo	应用领域
恩智浦 - NXP		晶体晶体管
页数	文件大小	规格书
7页	78K
描述
PowerMOS transistor Logic level FET

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BUK562-100A 数据手册

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level FET

BUK562-100A

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode logic

level field-effect power transistor in a

plastic envelope suitable for surface

mount applications.

The device is intended for use in

Switched Mode Power Supplies

(SMPS), motor control, welding,

DC/DC and AC/DC converters, and in

automotive and general purpose

switching applications.

SYMBOL

PARAMETER

MAX.

UNIT

V_DS

I_D

Drain-source voltage

Drain current (DC)

100

˚C

Ω

P_tot

T_j

Total power dissipation

Junction temperature

Drain-source on-state

175

0.28

R_DS(ON)

resistance;

V_GS= 5 V

PINNING - SOT404

PIN CONFIGURATION

SYMBOL

DESCRIPTION

gate

drain

source

mb drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DS

V_DGR

±V_GS

±V_GSM

I_D

Drain-source voltage

100

Drain-gate voltage

R_GS= 20 kΩ

Gate-source voltage

Non-repetitive gate-source voltage t_p≤ 50 µs

Drain current (DC)

T_mb= 25 ˚C

T_mb= 100 ˚C

T_mb= 25 ˚C

I_D

I_DM

Drain current (pulse peak value)

Total power dissipation

Storage temperature

Junction temperature

P_tot

T_stg

T_j

- 55

˚C

175

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX.

UNIT

R_{th j-mb}

R_{th j-a}

Thermal resistance junction to

2.5

K/W

mounting base

Thermal resistance junction to

ambient

minimum footprint,

FR4 board (see fig. 18).

K/W

February 1996

Rev 1.000

12 3 4 5 6 7

中文翻译

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