BUJ105AB

更新时间： 2024-01-07 04:04:57

品牌	Logo	应用领域
恩智浦 - NXP		晶体晶体管功率双极晶体管开关
页数	文件大小	规格书
7页	69K
描述
Silicon Diffused Power Transistor

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技术参数
数据手册

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BUJ105AB 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	,	Reach Compliance Code：	unknown
风险等级：	5.66	Is Samacsys：	N
最大集电极电流 (IC)：	6 A	配置：	Single
最小直流电流增益 (hFE)：	10	JESD-609代码：	e0
最高工作温度：	150 °C	极性/信道类型：	NPN
最大功率耗散 (Abs)：	26 W	子类别：	Other Transistors
表面贴装：	NO	端子面层：	Tin/Lead (Sn/Pb)
Base Number Matches：	1

BUJ105AB 数据手册

Philips Semiconductors

Product specification

Silicon Diffused Power Transistor

BUJ105AB

GENERAL DESCRIPTION

High-voltage, high-speed planar-passivated npn power switching transistor in SOT404 (D²-PAK) surface-mount

package intended for use in high frequency electronic lighting ballast applications, converters, inverters, switching

regulators, motor control systems, etc.

QUICK REFERENCE DATA

SYMBOL PARAMETER

CONDITIONS

TYP. MAX. UNIT

V_CESM

V_CBO

V_CEO

I_C

Collector-emitter voltage peak value

V_BE= 0 V

700

400

Collector-Base voltage (open emitter)

Collector-emitter voltage (open base)

Collector current (DC)

I_CM

Collector current peak value

Total power dissipation

Collector-emitter saturation voltage

P_tot

T_mb≤ 25 ˚C

125

1.0

V_CEsat

h_FEsat

t_f

I_C= 4.0 A;I_B= 0.8 A

I_C= 4.0 A; V_CE= 5 V

I_C= 5 A; I_B1= 1 A

0.3

Fall time

PINNING - SOT404

PIN CONFIGURATION

SYMBOL

DESCRIPTION

base

collector

emitter

mb collector

LIMITING VALUES8

Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN. MAX. UNIT

V_CESM

V_CEO

V_CBO

I_C

Collector to emitter voltage

V_BE= 0 V

700

400

700

Collector to emitter voltage (open base)

Collector to base voltage (open emitter)

Collector current (DC)

I_CM

Collector current peak value

Base current (DC)

Base current peak value

Total power dissipation

Storage temperature

Junction temperature

I_B

I_BM

P_tot

T_stg

T_j

125

150

T_mb≤ 25 ˚C

˚C

-65

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

TYP. MAX. UNIT

R_{th j-mb}

Thermal resistance junction to mounting

base

1.0

K/W

R_{th j-a}

Thermal resistance junction to ambient

minimum footprint, FR4 board

K/W

October 2001

Rev 1.000

12 3 4 5 6 7

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