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BU4081B-E2 PDF预览

BU4081B-E2

更新时间: 2024-11-04 06:44:35
品牌 Logo 应用领域
罗姆 - ROHM 栅极逻辑集成电路光电二极管
页数 文件大小 规格书
22页 494K
描述
High Voltage CMOS Logic ICs

BU4081B-E2 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.65Is Samacsys:N
系列:4000/14000/40000JESD-30 代码:R-PDIP-T14
长度:19.4 mm逻辑集成电路类型:AND GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):160 ns
认证状态:Not Qualified最大供电电压 (Vsup):16 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

BU4081B-E2 数据手册

 浏览型号BU4081B-E2的Datasheet PDF文件第2页浏览型号BU4081B-E2的Datasheet PDF文件第3页浏览型号BU4081B-E2的Datasheet PDF文件第4页浏览型号BU4081B-E2的Datasheet PDF文件第5页浏览型号BU4081B-E2的Datasheet PDF文件第6页浏览型号BU4081B-E2的Datasheet PDF文件第7页 
General-purpose CMOS Logic IC Series (BU4S,BU4000B Series)  
High Voltage CMOS Logic ICs  
<Logic Gate>  
BU4001B/F,BU4011B/F/FV,BU4030B/F,BU4070B/F,  
BU4081B/F/FV,BU4093B/F/FV,BU4069UB/F/FV,BU4584B/F/FV  
No.09050EAT03  
Description  
BU4001B series ICs are 2-input positive logic NOR gates, each with four built-in circuits. A buffer achieved by an inverter  
added at the gate output improves the input / output propagation characteristics and minimizes variation in the propagation  
time caused by an increase in the load capacitance. BU4011B series ICs are 2-input positive logic NAND gates. Four  
circuits are contained on a single chip. An inverter-based buffer is included at the gate output, enabling improved input /  
output propagation characteristics, and an increased load capacitance minimizes fluctuations in the propagation time.  
BU4030B and BU4070B series ICs are exclusive OR gates, each with four built-in circuits. An inverter-based buffer was  
incorporated at the gate output for enhanced I/O voltage characteristics, and the load capacitance has been increased in  
order to minimize fluctuations in the propagation time. BU4081B series are 2-input positive logic AND gates with four circuits  
mounted on a single chip. An inverter-type buffer was added to the gate output, improving input/output transmission speed,  
and an increased load capacitance suppresses fluctuations in the transmission time. BU4093B series ICs are 4-circuit,  
2-input NAND gates whose input pins all have a Schmitt trigger function. BU4069UB series ICs are 6-circuit inverters with no  
buffers. A single-stage gate configuration reduces propagation time. BU4584B series ICs are inverter-type Schmitt trigger  
circuits, each incorporating 6 circuits in a single chip.  
Features  
1) Low power consumption  
2) Broad operating supply voltage range: 3V to 16V  
3) High input impedance  
4) High fan out  
5) L-TTL2 and LS-TTL1 inputs can be directly driven  
6) All outputs are equipped with buffers (except for BU4069UB)  
Applications  
These products are suitable for applications requiring low power consumption and a high degree of noise tolerance  
The BU4030B/BU4070B series can be used in digital comparators and parity circuits  
The BU4093B series are suitable as line receivers, waveform shaping and multi-vibrators, etc.  
The BU4584B series can be used in waveform shaping circuits for inputs with a slow rise time and fall time  
Lineup  
4
NOR  
BU4001B/  
BU4001F  
High Voltage CMOS Logic  
Logic Gate  
(Quad 2-input NOR gate)  
(Quad 2-input NAND gate)  
(Quad exclusive OR gate)  
gate  
circuits  
BU4011B/  
BU4011B F/  
BU4011B FV  
NAND  
gate  
4
circuits  
EXOR  
gate  
4
BU4030B/  
BU4030B F  
circuits  
EXOR  
BU4070B/  
BU4070B F  
4
(Quad exclusive OR gate)  
(Quad 2-input AND gate)  
(Quad 2-input NAND Schmitt trigger)  
(Hex inverter)  
gate  
circuits  
BU4081B/  
BU4081F/  
BU4081FV  
BU4093B/  
BU4093B F/  
BU4093B FV  
BU4069UB/  
BU4069UB F/  
BU4069UB FV  
BU4584B/  
AND  
gate  
4
circuits  
NAND  
gate  
4
circuits  
INV  
gate  
6
circuits  
INV  
gate  
6
BU4584BF/  
BU4584BFV  
(Hex Schmitt trigger inverter)  
circuits  
www.rohm.com  
© 2009 ROHM Co., Ltd. All rights reserved.  
2009.06 - Rev.A  
1 / 21  
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