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BU-65145D2-460Q PDF预览

BU-65145D2-460Q

更新时间： 2024-11-25 23:37:11
品牌 Logo 应用领域
其他 - ETC 控制器
页数 文件大小 规格书
24页 221K
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Controller Miscellaneous - Datasheet Reference

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BU-65145D2-460Q 数据手册

 浏览型号BU-65145D2-460Q的Datasheet PDF文件第2页浏览型号BU-65145D2-460Q的Datasheet PDF文件第3页浏览型号BU-65145D2-460Q的Datasheet PDF文件第4页浏览型号BU-65145D2-460Q的Datasheet PDF文件第5页浏览型号BU-65145D2-460Q的Datasheet PDF文件第6页浏览型号BU-65145D2-460Q的Datasheet PDF文件第7页 
BU-6 5 1 4 2 a n d BUS -6 5 1 4 2 S ERIES  
MIL-S TD-1 5 5 3 DUAL REDUNDANT  
REMOTE TERMINAL HYBRID  
DESCRIPTION  
FEATURES  
The BUS-65142 Series is a com- Error detection and recovery are  
plete dual redundant MIL-STD- enhanced by BUS-65142 Series  
1553 Remote Terminal Unit (RTU) special features. A 14-bit built-in-  
packaged in a small 1.9" x 2.1" test word register stores RTU infor-  
hybrid. The device is based upon mation, and sends it to the Bus  
two DDC custom ICs, which Controller in response to the Mode  
includes two monolithic bi-polar low Command Transmit Bit Word. The  
power transceivers and one CMOS BUS-65142 Series performs contin-  
protocol containing data buffers uous on-line wraparound self-test,  
and timing control logic. It supports and provides four error flags to the  
all 13 mode codes for dual redun- host CPU. Inputs are provided for  
dant operation, any combinaion of host CPU control of 6 bits of the  
Complete Intergrated Remote  
Terminal Including:  
–Dual Low-Power Transceivers  
–Complete RT Protocol  
•
Direct Interface to Systems With  
No Processor  
•
•
•
•
Tolerant Version  
Radiation  
Available  
which can be illegalized.  
RTU Status Word.  
Space Qualified Version  
Available  
Parallel data transfers are accom- Its small hermetic package, -55°C  
plished with a DMA type handshak- to +125°C operating temperature  
ing, compatible with most CPU range, and complete RTU operation  
types. Data transfers to/from mem- make the BUS-65142 ideal for most  
ory are simplified by the latched MIL-STD-1553 applications requir-  
command word and word count out- ing hardware or microprocessor  
High Reliability Screening  
Available  
puts.  
subsystems.  
ENCODER/  
DECODER  
DATA  
BUS A  
BIT  
BUFFER  
TRANSCEIVER  
DB0-DB15  
BUF ENA  
PROCESSOR  
DTREQ  
DTGRT  
DTACK  
DTSTR  
R/W  
TRANSFER  
CONTROLS  
WATCHDOG  
TIMEOUT  
CURRENT  
WORD  
COUNTER  
ENCODER/  
DECODER  
DATA  
BUS B  
BIT  
TRANSCEIVER  
PROCESSOR  
M
U
X
A0-A4  
PROTOCOL  
SEQUENCER  
AND  
CONTROL  
LOGIC  
COMMAND  
LATCH  
A5-A10  
DAT/CMD  
ILL CMD (ME)  
SS REQ  
RT ADDRESS  
+
PARITY  
STATUS  
ADBC  
RT FLAG  
SS BUSY  
SS FLAG  
REGISTER  
16 MHz CLOCK  
MESS ERR  
RT FAIL  
ERROR FLAGS  
TIMING FLAGS  
HS FAIL  
RTADD ERR  
NBGT  
INCMD  
BITEN  
STATEN  
GBR  
DDC CUSTOM CHIP  
FIGURE 1. BUS-65142 SERIES BLOCK DIAGRAM  
1988, 1999 Data Device Corporation  
©
1234567...24

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