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BS62LV1024JIG70 PDF预览

BS62LV1024JIG70

更新时间: 2024-11-20 03:11:55
品牌 Logo 应用领域
BSI 静态存储器光电二极管
页数 文件大小 规格书
11页 525K
描述
Standard SRAM, 128KX8, 70ns, CMOS, PDSO32

BS62LV1024JIG70 数据手册

 浏览型号BS62LV1024JIG70的Datasheet PDF文件第2页浏览型号BS62LV1024JIG70的Datasheet PDF文件第3页浏览型号BS62LV1024JIG70的Datasheet PDF文件第4页浏览型号BS62LV1024JIG70的Datasheet PDF文件第5页浏览型号BS62LV1024JIG70的Datasheet PDF文件第6页浏览型号BS62LV1024JIG70的Datasheet PDF文件第7页 
Very Low Power/Voltage CMOS SRAM  
128K X 8 bit  
BSI  
BS62LV1024  
• Easy expansion with CE2, CE1, and OE options  
„ FEATURES  
• Wide Vcc operation voltage : 2.4V ~ 5.5V  
• Very low power consumption :  
„ DESCRIPTION  
The BS62LV1024 is a high performance, very low power CMOS  
Static Random Access Memory organized as 131,072 words by 8 bits  
and operates from a wide range of 2.4V to 5.5V supply voltage.  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current of  
0.02uA and maximum access time of 70ns in 3V operation.  
Easy memory expansion is provided by an active LOW chip  
enable (CE1), an active HIGH chip enable (CE2), and active LOW  
output enable (OE) and three-state output drivers.  
Vcc = 3.0V C-grade : 20mA (Max.) operating current  
I- grade : 25mA (Max.) operating current  
0.02uA (Typ.) CMOS standby current  
Vcc = 5.0V C-grade : 35mA (Max.) operating current  
I- grade : 40mA (Max.) operating current  
0.4uA (Typ.) CMOS standby current  
• High speed access time :  
-70  
70ns (Max.) at Vcc = 3.0V  
• Automatic power down when chip is deselected  
• Three state outputs and TTL compatible  
• Fully static operation  
The BS62LV1024 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
The BS62LV1024 is available in JEDEC standard 32 pin 450mil Plastic  
SOP, 300mil Plastic SOJ , 600mil Plastic DIP, 8mmx13.4mm STSOP,  
8mmx13.4mm Reverse STSOP and 8mmx20mm TSOP.  
• Data retention supply voltage as low as 1.5V  
„ PRODUCT FAMILY  
S P E E D  
P O W E R D IS S IPAT IO N  
(n s )  
P R O D U C T  
F A M ILY  
O P E R AT IN G  
T E M P E R AT U R E  
V c c  
R A N G E  
S ta n d b y  
(Ic c S B 1 , M a x )  
O p e ra tin g  
(Ic c , M a x )  
P K G T Y P E  
V c c = 3 V  
V c c = 5 V V c c = 3 V V c c = 5 V V c c = 3 V  
B S 6 2 LV 1 0 2 4 S C  
B S 6 2 LV 1 0 2 4 T C  
B S 6 2 LV 1 0 2 4 S T C  
B S 6 2 LV 1 0 2 4 P C  
B S 6 2 LV 1 0 2 4 J C  
S O P -3 2  
T S O P -3 2  
S T S O P -3 2  
P D IP -3 2  
0
O C to + 7 0 O C  
2 .4 V ~ 5 .5 V  
7 0  
3 .0 u A  
1 .0 u A  
3 5 m A  
2 0 m A  
S O J -3 2  
R e v e rs e  
S T S O P -3 2  
S O P -3 2  
T S O P -3 2  
S T S O P -3 2  
P D IP -3 2  
B S 6 2 LV 1 0 2 4 R C  
B S 6 2 LV 1 0 2 4 S I  
B S 6 2 LV 1 0 2 4 T I  
B S 6 2 LV 1 0 2 4 S T I  
B S 6 2 LV 1 0 2 4 P I  
B S 6 2 LV 1 0 2 4 J I  
-4 0 O C to + 8 5 O C 2 .4 V ~ 5 .5 V  
7 0  
5 .0 u A  
1 .5 u A  
4 0 m A  
2 5 m A  
S O J -3 2  
R e v e rs e  
S T S O P -3 2  
B S 6 2 LV 1 0 2 4 R I  
„ PIN CONFIGURATIONS  
„ BLOCK DIAGRAM  
NC  
A16  
A14  
A12  
A7  
1
VCC  
A15  
CE2  
WE  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
1
2
3
4
5
6
7
8
A11  
A9  
A8  
OE  
2
A6  
A7  
A12  
A14  
A16  
A15  
A13  
A8  
A10  
CE1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
GND  
DQ2  
DQ1  
DQ0  
A0  
3
4
A13  
WE  
CE2  
A15  
VCC  
NC  
A16  
A14  
A12  
A7  
Address  
5
A13  
A8  
Memory Array  
20  
1024  
Row  
Decoder  
A6  
6
BS62LV1024SC  
BS62LV1024SI  
BS62LV1024PC  
BS62LV1024PI  
BS62LV1024JC  
BS62LV1024JI  
Input  
BS62LV1024TC  
BS62LV1024STC  
BS62LV1024TI  
BS62LV1024STI  
A5  
7
A9  
1024 x 1024  
A4  
8
A11  
OE  
Buffer  
A3  
9
9
10  
11  
12  
13  
14  
15  
16  
A2  
A9  
A11  
10  
11  
12  
13  
14  
15  
16  
A10  
CE1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
A1  
A0  
1024  
DQ0  
DQ1  
DQ2  
GND  
A6  
A5  
A4  
A1  
A2  
A3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
8
Data  
Input  
Buffer  
8
Column I/O  
Write Driver  
Sense Amp  
8
8
Data  
Output  
Buffer  
128  
OE  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
1
2
3
4
5
6
7
8
A11  
A9  
A8  
A10  
CE1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
GND  
DQ2  
DQ1  
DQ0  
A0  
Column Decoder  
14  
A13  
WE  
CE2  
A15  
VCC  
NC  
A16  
A14  
A12  
A7  
CE2  
CE1  
WE  
BS62LV1024RC  
BS62LV1024RI  
Control  
Address Input Buffer  
9
OE  
Vdd  
Gnd  
10  
11  
12  
13  
14  
15  
16  
A5 A4 A3 A2 A1 A0 A10  
A1  
A2  
A3  
A6  
A5  
A4  
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.  
Revision 2.4  
Jan. 2004  
R0201-BS62LV1024  
1

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