Very Low Power/Voltage CMOS SRAM
64K X 16 bit
BSI
BS616LV1010
DESCRIPTION
FEATURES
• Very low operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
The BS616LV1010 is a high performance, very low power CMOS Static
Random Access Memory organized as 65,536 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.02uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
Vcc = 3.0V
C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.02uA (Typ.) CMOS standby current
C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
Vcc = 5.0V
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
The BS616LV1010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1010 is available in the JEDEC standard 44-pin TSOP
Type II and 48-pin BGA package.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
PRODUCT
FAMILY
OPERATING
Vcc
STANDBY
Operating
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
TEMPERATURE
RANGE
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
BS616LV1010EC
TSOP2-44
+0 O C to +70 O
-40 O C to +85O
C
C
2.4V ~ 5.5V
2.4V ~ 5.5V
70
3uA
5uA
0.5uA
35mA
40mA
20mA
BS616LV1010AC
BS616LV1010EI
BS616LV1010AI
BGA-48-0608
TSOP2-44
70
1.5uA
25mA
BGA-48-0608
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A5
A6
A7
OE
UB
LB
2
A3
3
A2
4
A1
5
A0
A8
6
CE
A13
A15
7
DQ0
DQ15
Address
8
DQ1
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
18
512
9
DQ2
A14
A12
A7
BS616LV1010EC
10
Input
DQ3
Row
Memory Array
512 x 2048
11
VCC
BS616LV1010EI
12
GND
Buffer
13
DQ4
Decoder
14
A6
A5
A4
DQ5
15
DQ6
16
DQ7
17
WE
18
A15
A8
2048
19
A14
A9
20
Data
A13
A10
16
16
16
21
Column I/O
A12
Input
A11
DQ0
22
NC
NC
Buffer
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
1
2
3
4
5
6
128
Data
16
A
B
C
D
E
F
LB
OE
UB
A0
A3
A1
A4
A2
NC
IO0
IO2
Output
Buffer
Column Decoder
DQ15
IO8
CE
14
CE
WE
OE
UB
IO9
IO10
IO11
IO12
IO13
NC
A5
A6
IO1
IO3
IO4
IO5
WE
A11
Control
Address Input Buffer
VSS
VCC
IO14
IO15
NC
NC
NC
A14
A12
A9
A7
VCC
VSS
IO6
IO7
NC
LB
A11 A9 A3 A2 A1
A0 A10
NC
A15
A13
A10
Vcc
Gnd
G
H
A8
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.2
April 2001
R0201-BS616LV1010
1