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BQ3285 PDF预览

BQ3285

更新时间: 2024-10-27 22:27:51
品牌 Logo 应用领域
德州仪器 - TI 时钟
页数 文件大小 规格书
22页 554K
描述
Real-Time Clock RTC

BQ3285 数据手册

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bq3285  
Real-Time Clock (RTC)  
General Description  
Features  
Calendar in day of the week, day  
of the month, months, and years,  
with automatic leap-year adjust-  
ment  
Direct clock/calendar replace-  
ment for IBM® AT-compatible  
computers and other applications  
The CMOS bq3285 is a low-power  
microprocessor peripheral providing  
a time-of-day clock and 100-year cal-  
endar with alarm features and bat-  
tery operation. Other features in-  
clude three maskable interrupt  
sources, square wave output, and 114  
bytes of general nonvolatile storage.  
Time of day in seconds, minutes,  
Functionally compatible with the  
and hours  
DS1285  
- 12- or 24-hour format  
- Optional daylight saving  
- Closely matches MC146818A  
pin configuration  
adjustment  
The bq3285 write-protects the clock,  
calendar, and storage registers during  
power failure. A backup battery  
then maintains data and operates the  
clock and calendar.  
114 bytes of general nonvolatile  
Programmable square wave out-  
storage  
put  
160ns cycle time allows fast bus  
Three individually maskable in-  
operation  
terrupt event flags:  
Selectable Intel or Motorola bus  
- Periodic rates from 122µs to  
The bq3285 is a fully compatible  
real-time clock for IBM AT com-  
patible computers and other appli-  
cations. The only external compo-  
nents are a 32.768kHz crystal and  
a backup battery  
timing  
500ms  
Less than 0.5µA load under bat-  
- Time-of-day alarm once per  
tery operation  
second to once per day  
- End-of-clock update cycle  
24-pin plastic DIP or SOIC  
14 bytes for clock/calendar and  
control  
BCD or binary format for clock  
and calendar data  
Pin Names  
Pin Connections  
AD0–AD7  
Multiplexed address/data  
input/output  
MOT  
CS  
Bus type select input  
Chip select input  
Address strobe input  
Data strobe input  
Read/write input  
MOT  
24  
1
V
CC  
SQW  
NC  
X1  
X2  
23  
22  
2
3
AS  
4
RCL  
BC  
DS  
AD  
AD  
AD  
AD  
AD  
AD  
AD  
21  
20  
19  
18  
17  
16  
15  
14  
13  
0
1
2
3
4
5
6
5
6
AD  
AD  
25  
24  
RCL  
BC  
0
1
5
R/W  
INT  
6
INT  
RST  
DS  
7
8
9
10  
11  
Interrupt request  
output  
AD  
AD  
AD  
AD  
23  
22  
21  
20  
19  
INT  
RST  
DS  
2
3
4
5
7
8
9
RST  
SQW  
RCL  
BC  
Reset input  
V
SS  
V
NC  
R/W  
SS  
Square wave output  
RAM clear input  
3V backup cell input  
Crystal inputs  
No connect  
10  
11  
12  
R/W  
AS  
CS  
AD  
7
V
SS  
X1–X2  
NC  
28-Pin PLCC  
PN328501.eps  
24-Pin DIP or SOIC  
PN328501.eps  
VCC  
VSS  
+5V supply  
Ground  
Jan. 1999 E  
1

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