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BQ2502 PDF预览

BQ2502

更新时间: 2024-02-14 22:26:49
品牌 Logo 应用领域
德州仪器 - TI 装置
页数 文件大小 规格书
12页 85K
描述
Integrated Backup Unit

BQ2502 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:0.600 INCH, DIP-12Reach Compliance Code:unknown
风险等级:5.91可调阈值:YES
模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUITJESD-30 代码:S-PDMA-P12
JESD-609代码:e0长度:18.415 mm
信道数量:1功能数量:1
端子数量:12最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP12,.6
封装形状:SQUARE封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:8.53 mm
子类别:Power Management Circuits最大供电电流 (Isup):6 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:PIN/PEG
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:18.415 mm
Base Number Matches:1

BQ2502 数据手册

 浏览型号BQ2502的Datasheet PDF文件第2页浏览型号BQ2502的Datasheet PDF文件第3页浏览型号BQ2502的Datasheet PDF文件第4页浏览型号BQ2502的Datasheet PDF文件第5页浏览型号BQ2502的Datasheet PDF文件第6页浏览型号BQ2502的Datasheet PDF文件第7页 
bq2502  
Integrated Backup Unit  
Features  
The external SRAMs are write-pro-  
General Description  
Power monitoring, backup supply,  
a n d swit ch in g for 3V ba t t er y-  
backup applications  
tected until a power-valid condition  
exists. The reset output provides  
power-fail and power-on resets for the  
system.  
The CMOS bq2502 Integrated Backup  
Unit provides all the necessary func-  
t ion s for con ver t in g on e or t wo  
ba n ks of st a n da r d CMOS SRAM  
into nonvolatile read/write memory.  
Write-protect control  
During power-valid operation, the  
in pu t decoder select s on e of t wo  
banks of SRAM.  
Input decoder for control of up to  
2 banks of SRAM  
A precision comparator monitors the 5V  
V
input for an out-of-tolerance condi-  
CC  
3-volt backup power output  
The internal lithium cell is initially  
electrically isolated, protecting the  
battery from accidental discharge.  
Connection to the battery is made  
only after the first application of  
tion. When out of tolerance is detected,  
the two conditioned chip-enable outputs  
are forced inactive to write-protect both  
banks of SRAM.  
In t er n a l 130m Ah lit h iu m -coin  
cell  
Reset output for system power-on  
reset  
V
CC  
.
Power for the external SRAMs is  
switched from the V  
supply to the  
CC  
L e s s t h a n 1 0 n s ch ip -e n a b le  
internal battery-backup supply as  
d eca ys. On s u bs equ en t  
supply is auto-  
propagation delay  
V
a
C C  
power-up, the V  
OUT  
5% or 10% supply operation  
matically switched from the internal  
lithium supply to the V supply.  
CC  
Pin Names  
Pin Connections  
VOUT  
Supply output  
RST  
Reset output  
1
2
3
4
5
6
V
V
12  
11  
10  
9
8
7
THS  
CE  
Threshold select input  
chip-enable active low input  
Conditioned chip-enable outputs  
CC  
CE  
OUT  
NC  
A
NC  
CE  
CE  
NC  
RST  
CON1  
CON2  
CECON1  
CECON2  
,
THS  
V
SS  
A
Bank select input  
No connect  
NC  
VCC  
VSS  
12-Pin 600-mil DIP Module  
5-volt supply input  
Ground  
PN250201.eps  
Functional Description  
Two banks of CMOS static RAM can be battery-backed  
If THS is tied to V  
, power-fail detection occurs at  
OUT  
4.37V typical for 10% supply operation. The THS pin  
must be tied to V or V for proper operation.  
using the V  
from the bq2502. As the voltage input V  
and conditioned chip-enable output pins  
OUT  
slews down  
SS  
OUT  
CC  
during a power failure, the two conditioned chip-enable  
ou t pu t s, CE a n d CE , a r e for ced in a ct ive  
independent of the chip-enable input CE.  
If a memory access is in process to any of the two exter-  
nal banks of SRAM during power-fail detection, that  
memory cycle continues to completion before the memory  
is write-protected. If the memory cycle is not terminated  
CON1  
CON2  
This activity unconditionally write-protects external SRAM  
within time t  
(150µs maximum), the two chip-enable  
as V  
falls to an out-of-tolerance threshold V . V  
PFD PFD  
is  
WPT  
CC  
outputs are unconditionally driven high, write-protecting  
the controlled SRAMs.  
selected by the threshold-select input pin, THS. If THS is  
tied to V , the power-fail detection occurs at 4.62V typical  
SS  
for 5% supply operation.  
Apr. 1991  
1

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