Datasheet
Termination Regulator for DDR-SDRAMs
BD3531F
General Description
Key Specifications
BD3531F is a termination regulator that complies with
JEDEC requirements for DDR-SDRAM. This linear
power supply uses a built-in N-channel MOSFET and
high-speed OP-AMPS specially designed to provide
excellent transient response. It has a sink/source
current capability up to 1.5A and has a power supply
bias requirement of 5.0V for driving the N-channel
MOSFET. By employing an independent reference
voltage input (VDDQ) and a feedback pin (VTTS), this
termination regulator provides excellent output voltage
accuracy and load regulation as required by JEDEC
standards. Additionally, BD3531F has a reference
power supply output (VREF) for DDR-SDRAM or for
memory controllers. Unlike the VTT output that goes to
“Hi-Z” state, the VREF output is kept unchanged when
EN input is changed to “Low”, making this IC suitable
for DDR-SDRAM under “Self Refresh” state.
Termination Input Voltage Range:
VCC Input Voltage Range:
Output Voltage:
1.0V to 5.5V
4.5V to 5.5V
1/2xVVDDQ V(Typ)
1.5A(Max)
Output Current:
High Side FET ON-Resistance:
Low side FET ON-Resistance:
Standby Current:
0.4Ω(Typ)
0.4Ω(Typ)
0.8mA (Typ)
Operating Temperature Range: -10°C to +100°C
Package
W(Typ) x D(Typ) x H(Max)
Features
Incorporates
a Push-Pull Power Supply for
Termination (VTT)
Incorporates a Reference Voltage Circuit (VREF)
Incorporates an Enabler
Incorporates an Undervoltage Lockout (UVLO)
Incorporates a Thermal Shutdown Protector (TSD)
Compatible with Dual Channel (DDR-II)
SOP8
5.00mm x 6.20mm x 1.71mm
Applications
Power supply for DDR I/II - SDRAM
Typical Application Circuit, Block Diagram
VTT_IN
VCC
VDDQ
VDDQ
VCC
VTT_IN
VCC
VCC
VCC
50kΩ
UVLO
Reference
Block
VTT
TSD
EN
UVLO
VCC
VTT
50kΩ
UVLO
TSD
TSD
VTTS
VREF
Thermal
EN
UVLO
Protection
½ x
Enable
EN
VDDQ
GND
○Product structure:Silicon monolithic integrated circuit ○This product has no designed protection against radioactive rays
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