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BCM5222KPFa PDF预览

BCM5222KPFa

更新时间: 2024-11-19 01:13:03
品牌 Logo 应用领域
博通 - BOARDCOM 局域网(LAN)标准
页数 文件大小 规格书
76页 1084K
描述
Dual Port 10/100BASE-TX IEEE 802.3u Fast Ethernet Transceiver

BCM5222KPFa 数据手册

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Preliminary Data Sheet  
BCM5222  
Dual Port 10/100BASE-TX IEEE 802.3u Fast Ethernet Transceiver  
GENERAL DESCRIPTION  
FEATURES  
The BCM5222 is a dual-port, low-power, 10/100BASE-  
TX transceiver targeting a number of applications  
requiring intelligent power management and robust  
network tolerance. The BCM5222 operates using a 1.8V  
and 3.3V supply. The devices contain two full-duplex  
10BASE-T/100BASE-TX Fast Ethernet transceivers,  
which perform all of the physical layer interface functions  
for 10BASE-T Ethernet on CAT 3, 4, and 5 unshielded  
twisted pair (UTP) cable and 100BASE-TX Fast Ethernet  
on CAT 5 UTP cable.  
Dual Port 10/100BASE-TX IEEE 802.3u Fast  
Ethernet Transceiver  
Power Consumption: <180 mW/port  
Unique Energy Detection Circuit to Enable Intelligent  
Power Management  
HP Auto-MDIX  
Cable Length Indication  
Cable Noise Level Indication  
Cable length greater than 140 meters  
Well Under 10 PPM defect ratio quality  
Industrial Temperature Range (-40 to 85C)  
MII/7-wire serial interface  
The BCM5222 is a highly integrated solution combining  
a digital adaptive equalizer, ADC, phase lock loop, line  
driver, encoder, decoder and all the required support  
circuitry into a single monolithic CMOS chip. It complies  
fully with the IEEE 802.3u specification, including the  
Media Independent Interface (MII) and Auto-Negotiation  
subsections.  
IEEE 1149.1 (JTAG) Scan Chain Support  
MII Management Via Serial Port  
100-pin PQFP and 100-pin fpBGA packages  
APPLICATIONS  
The effective use of digital technology in the BCM5222  
design results in robust performance over a broad range  
of operating scenarios. Problems inherent to mixed-  
signal implementations, such as analog offset and on-  
chip noise, are eliminated by employing field proven  
digital adaptive equalization and digital clock recovery  
techniques.  
IP Phones  
Backplane Bus Communication  
Embedded Telecom  
Print Servers  
TXD[1:2]  
TXEN[1:2]  
TXER[1:2]  
TXC[1:2]  
4
Multimode  
Xmt DAC  
TD±[1:2]  
10BASE-T  
PCS  
Auto  
MDIX  
Baseline  
Wander  
COL[1:2]  
RXC[1:2]  
Correction  
100BASE-TX  
PCS  
CRS[1:2]  
RXDV[1:2]  
RXER[1:2]  
RXD[1:2]  
Digital  
Adaptive  
Equalizer  
RD±[1:2]  
ADC  
4
CRS/Link  
Detection  
ACTLED#[1:2]  
LNKLED#[1:2]  
SPDLED#[1:2]  
FDXLED#[1:2]  
Auto-Negotiation  
/Link Integrity  
LED  
Drivers  
Clock  
Generator  
XTALO  
XTALI  
Clock  
Recovery  
MODES  
Bias  
Generator  
RDAC  
JTAG  
MII  
MDC  
MII  
Registers  
Mgmt  
JTAG  
Test Logic  
MDIO  
Control  
5
Figure 1: Functional Block Diagram  
5222-DS02-405-R  
7/20/04  
16215 Alton Parkway P.O. Box 57013 • Irvine, CA 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710  

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