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AZ10LVEL33D PDF预览

AZ10LVEL33D

更新时间: 2024-11-10 04:33:23
品牌 Logo 应用领域
AZM 逻辑集成电路光电二极管
页数 文件大小 规格书
10页 128K
描述
ECL/PECL ±4 Divider

AZ10LVEL33D 技术参数

是否Rohs认证: 不符合生命周期:Contact Manufacturer
包装说明:SOP, SOP8,.25Reach Compliance Code:compliant
风险等级:5.83Is Samacsys:N
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
逻辑集成电路类型:PRESCALER端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:-5.2 V
认证状态:Not Qualified子类别:Prescaler/Multivibrators
表面贴装:YES技术:ECL10K
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

AZ10LVEL33D 数据手册

 浏览型号AZ10LVEL33D的Datasheet PDF文件第2页浏览型号AZ10LVEL33D的Datasheet PDF文件第3页浏览型号AZ10LVEL33D的Datasheet PDF文件第4页浏览型号AZ10LVEL33D的Datasheet PDF文件第5页浏览型号AZ10LVEL33D的Datasheet PDF文件第6页浏览型号AZ10LVEL33D的Datasheet PDF文件第7页 
ARIZONA MICROTEK, INC.  
AZ10LVEL33  
AZ100LVEL33  
ECL/PECL ÷4 Divider  
PACKAGE AVAILABILITY  
FEATURES  
PACKAGE  
PART NUMBER  
MARKING NOTES  
Green / RoHS Compliant /  
MLP 8 (2x2) Green  
/ RoHS Compliant /  
Lead (Pb) Free  
C3G  
<Date Code>  
Lead (Pb) Free package available  
Operating Range of 3.0V to 5.5V  
470ps Propagation Delay  
AZ100LVEL33NG  
1,2  
AZM  
MLP 16 (3x3)  
AZ10/100LVEL33L  
L33  
1,2  
4.0GHz Toggle Frequency  
<Date Code>  
AZM10  
LVEL33  
AZM100  
LVEL33  
AZT  
LV33  
AZH  
LV33  
Internal Input Pulldown Resistors  
Direct Replacement for ON Semiconductor  
MC10EL33, MC100EL33,  
SOIC 8  
AZ10LVEL33D  
AZ100LVEL33D  
AZ10LVEL33T  
AZ100LVEL33T  
1,2,3  
1,2,3  
1,2,3  
1,2,3  
SOIC 8  
and MC100LVEL33  
Transistor Count = 91 Devices  
IBIS Model Files Available on Arizona  
Microtek Web Site  
TSSOP 8  
TSSOP 8  
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K  
parts) Tape & Reel.  
2
3
Date code format: “Y” or “YY” for year followed by “WW” for week.  
Date code “YWW” or “YYWW” on underside of part.  
DESCRIPTION  
The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q  
Low, Q¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET  
allows for the synchronization of multiple LVEL33’s in a system.  
The LVEL33 provides a VBB output for single-end use or a DC bias reference for AC coupling to the device.  
For single-ended input applications, the VBB reference should be connected to one side of the CLK/C¯¯L¯K¯ differential  
input pair. The input signal is then fed to the other CLK/C¯¯L¯K¯ input. The VBB pin can support 1.0mA sink/source  
current. When used, the VBB pin should be bypassed to ground via a 0.01μF capacitor.  
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.  
LOGIC DIAGRAM  
PIN DESCRIPTION  
RESET  
R
PIN  
FUNCTION  
Q
Q
CLK, C¯L¯¯K Clock Inputs  
RESET  
VBB  
Q, Q¯  
VCC  
Asynchronous Reset  
Reference Voltage Output  
Data Outputs  
÷4  
CLK  
CLK  
Positive Supply  
VEE  
Negative Supply  
VBB  
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541  
www.azmicrotek.com  

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