ARIZONA MICROTEK, INC.
AZ10LVEL11
AZ100LVEL11
ECL/PECL 1:2 Differential Fanout Buffer
PACKAGE AVAILABILITY
FEATURES
PACKAGE
PART NUMBER
MARKING NOTES
•
•
•
•
•
•
265ps Propagation Delay
AZM10
LVEL11
SOIC 8
AZ10LVEL11D
1,2
5ps Skew Between Outputs
High Bandwidth Output Transitions
Internal Input Pulldown Resistors
Operating Range of 3.0V to 5.5V
Direct Replacement for ON Semi
MC100LVEL11, MC10EL11
& MC100EL11
AZM100
LVEL11
SOIC 8
AZ100LVEL11D
AZ10LVEL11D+
1,2
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
AZM10+
1,2
LVEL11
AZM100+
1,2
AZ100LVEL11D+
LVEL11
•
Transistor Count = 51
AZT
1,2
TSSOP 8
TSSOP 8
AZ10LVEL11T
AZ100LVEL11T
LV11
AZH
LV11
1,2
TSSOP 8 RoHS
Compliant / Lead
(Pb) Free
AZH+
1,2
AZ100LVEL11T+
LV11
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code “YWW” or “YYWW” on underside of part.
DESCRIPTION
2
The AZ10/100LVEL11 is a differential 1:2 fanout gate. The device is functionally similar to the E111 device
but with higher performance capabilities. Having within-device skews and output transition times significantly
improved over the E111, the AZ10/100LVEL11 is ideally suited for those applications that require the ultimate in
AC performance.
The differential inputs of the AZ10/100LVEL11 employ clamping circuitry to maintain stability under open
input conditions. If the inputs are left open, the Q outputs will go LOW.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
VCC
Q0 1
8
PIN DESCRIPTION
PIN
FUNCTION
Data Inputs
Q0, Q¯¯0, Q1, Q¯¯1 Data Outputs
2
3
4
Q0
Q1
Q1
7
6
D
D
D, D¯
VCC
VEE
Positive Supply
Negative Supply
VEE
5
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com