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AZ10LVE111FN PDF预览

AZ10LVE111FN

更新时间： 2024-11-10 04:33:23
品牌 Logo 应用领域
AZM 时钟驱动器
页数 文件大小 规格书
6页 85K
描述
ECL/PECL 1:9 Differential Clock Driver

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中文翻译

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AZ10LVE111FN 技术参数

是否Rohs认证：不符合生命周期：Contact Manufacturer
包装说明：QCCJ, LDCC28,.5SQReach Compliance Code：compliant
风险等级：5.88Is Samacsys：N
JESD-30 代码：S-PQCC-J28JESD-609代码：e0
端子数量：28最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
电源：-5.2 VProp。Delay @ Nom-Sup：0.7 ns
认证状态：Not Qualified子类别：Clock Drivers
表面贴装：YES技术：ECL10K
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUADBase Number Matches：1

AZ10LVE111FN 数据手册

 浏览型号AZ10LVE111FN的Datasheet PDF文件第2页浏览型号AZ10LVE111FN的Datasheet PDF文件第3页浏览型号AZ10LVE111FN的Datasheet PDF文件第4页浏览型号AZ10LVE111FN的Datasheet PDF文件第5页浏览型号AZ10LVE111FN的Datasheet PDF文件第6页 
ARIZONA MICROTEK, INC.  
AZ10LVE111  
AZ100LVE111  
ECL/PECL 1:9 Differential Clock Driver  
FEATURES  
PACKAGE AVAILABILITY  
•
•
•
•
•
•
•
Operating Range of 3.0V to 5.5V  
Low Skew  
Guaranteed Skew Spec  
Differential Design  
PACKAGE  
PART NO.  
MARKING NOTES  
AZ10  
PLCC 28  
LVE111  
<Date Code>  
AZ100  
LVE111  
<Date Code>  
AZ100+  
LVE111  
1,2  
1,2  
1,2  
AZ10LVE111FN  
VBB Output  
75kΩ Internal Pulldown Resistors  
Direct Replacement for ON  
Semiconductor MC100LVE111  
PLCC 28  
AZ100LVE111FN  
AZ100LVE111FN+  
PLCC 28 RoHS  
Compliant / Lead  
(Pb) Free  
<Date Code>  
1
2
Add R2 at end of part number for 13 inch (750 parts) Tape & Reel.  
Date code format: “YY” for year followed by “WW” for week.  
DESCRIPTION  
The AZ10/100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The  
IN signal is fanned-out to nine identical differential outputs.  
The AZ100LVE111 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the  
device. For single–ended input applications, the VBB reference should be connected to one side of the IN/I¯N¯  
differential input pair. The input signal is then fed to the other IN/I¯N¯ input. When used, the VBB pin should be  
bypassed to ground via a 0.01μF capacitor.  
The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and  
layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process  
control limits that ensure consistent tpd distributions from lot-to-lot. The net result is a dependable, guaranteed low  
skew device.  
To ensure that the tight skew specification is met, both sides of the differential output must be terminated into  
50Ω, even if only one side is used. In most applications all nine differential pairs will be used and therefore  
terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on  
the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side, in order to maintain  
minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of  
the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin.  
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.  
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541  
www.azmicrotek.com  
123456

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