Datasheet > AZ10LVE111

AZ10LVE111

更新时间： 2024-11-10 04:33:23

品牌	Logo	应用领域
AZM		时钟驱动器
页数	文件大小	规格书
6页	85K
描述
ECL/PECL 1:9 Differential Clock Driver

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AZ10LVE111 数据手册

ARIZONA MICROTEK, INC.

AZ10LVE111

AZ100LVE111

ECL/PECL 1:9 Differential Clock Driver

FEATURES

PACKAGE AVAILABILITY

•

Operating Range of 3.0V to 5.5V

Low Skew

Guaranteed Skew Spec

Differential Design

PACKAGE

PART NO.

MARKING NOTES

AZ10

PLCC 28

LVE111

AZ100

LVE111

AZ100+

LVE111

1,2

AZ10LVE111FN

V_BBOutput

75kΩ Internal Pulldown Resistors

Direct Replacement for ON

Semiconductor MC100LVE111

PLCC 28

AZ100LVE111FN

AZ100LVE111FN+

PLCC 28 RoHS

Compliant / Lead

(Pb) Free

Add R2 at end of part number for 13 inch (750 parts) Tape & Reel.

Date code format: “YY” for year followed by “WW” for week.

DESCRIPTION

The AZ10/100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The

IN signal is fanned-out to nine identical differential outputs.

The AZ100LVE111 provides a V_BBoutput for single-ended use or a DC bias reference for AC coupling to the

device. For single–ended input applications, the V_BBreference should be connected to one side of the IN/I¯N¯

differential input pair. The input signal is then fed to the other IN/I¯N¯ input. When used, the V_BBpin should be

bypassed to ground via a 0.01μF capacitor.

The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and

layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process

control limits that ensure consistent t_pddistributions from lot-to-lot. The net result is a dependable, guaranteed low

skew device.

To ensure that the tight skew specification is met, both sides of the differential output must be terminated into

50Ω, even if only one side is used. In most applications all nine differential pairs will be used and therefore

terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on

the same package side (i.e. sharing the same V_CCO) as the pair(s) being used on that side, in order to maintain

minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of

the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin.

NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541

www.azmicrotek.com

12 3 4 5 6

中文翻译

下载PDF

与AZ10LVE111相关器件

型号	品牌	获取价格	描述	数据表
AZ10LVE111E	AZM	获取价格	ECL/PECL 1:9 Differential Clock Driver with Enable
AZ10LVE111EFN	AZM	获取价格	ECL/PECL 1:9 Differential Clock Driver with Enable
AZ10LVE111FN	AZM	获取价格	ECL/PECL 1:9 Differential Clock Driver
AZ10LVEL11	AZM	获取价格	ECL/PECL 1:2 Differential Fanout Buffer
AZ10LVEL11D	AZM	获取价格	ECL/PECL 1:2 Differential Fanout Buffer
AZ10LVEL11D+	AZM	获取价格	ECL/PECL 1:2 Differential Fanout Buffer
AZ10LVEL11T	AZM	获取价格	ECL/PECL 1:2 Differential Fanout Buffer
AZ10LVEL16	AZM	获取价格	ECL/PECL Differential Receiver
AZ10LVEL16D	AZM	获取价格	ECL/PECL Differential Receiver
AZ10LVEL16T	AZM	获取价格	ECL/PECL Differential Receiver

与AZ10LVE111相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

24
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

24
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

50
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

40

产品中心

服务支持

精选活动

关于我们

帮助中心

AZ10LVE111

AZ10LVE111 数据手册

与AZ10LVE111相关器件

与AZ10LVE111相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AZ10LVE111

AZ10LVE111 数据手册

与AZ10LVE111相关器件

与AZ10LVE111相关文章

您还可以找

您在本页遇到什么问题？