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AZ10EL31D PDF预览

AZ10EL31D

更新时间: 2024-09-21 04:33:23
品牌 Logo 应用领域
AZM 触发器
页数 文件大小 规格书
6页 78K
描述
ECL/PECL D Flip-Flop with Set and Reset

AZ10EL31D 技术参数

是否Rohs认证:不符合生命周期:Contact Manufacturer
包装说明:,Reach Compliance Code:compliant
风险等级:5.83Is Samacsys:N
Base Number Matches:1

AZ10EL31D 数据手册

 浏览型号AZ10EL31D的Datasheet PDF文件第2页浏览型号AZ10EL31D的Datasheet PDF文件第3页浏览型号AZ10EL31D的Datasheet PDF文件第4页浏览型号AZ10EL31D的Datasheet PDF文件第5页浏览型号AZ10EL31D的Datasheet PDF文件第6页 
ARIZONA MICROTEK, INC.  
AZ10EL31  
AZ100EL31  
ECL/PECL D Flip-Flop with Set and Reset  
FEATURES  
PACKAGE AVAILABILITY  
475ps Propagation Delay  
2.8GHz Toggle Frequency  
75kΩ Internal Input Pulldown Resistors  
Direct Replacement for ON Semiconductor  
MC10EL31 & MC100EL31  
PACKAGE  
SOIC 8  
SOIC 8  
TSSOP 8  
TSSOP 8  
PART NUMBER  
AZ10EL31D  
AZ100EL31D  
AZ10EL31T  
MARKING  
AZM10EL31  
AZM100EL31  
AZTEL31  
NOTES  
1,2  
1,2  
1,2  
1,2  
AZ100EL31T  
AZHEL31  
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)  
Tape & Reel.  
2
Date Code “YWW” on underside of part.  
DESCRIPTION  
The AZ10/100EL31 is a master-slave D flip-flop with set and reset. The device is functionally equivalent to the  
E131 device with higher performance capabilities. With propagation delays and output transition times significantly  
faster than the E131, the EL31 is ideally suited for those applications that require the ultimate in AC performance.  
Both set and reset inputs are asynchronous, level triggered signals. Data enters the master section of the flip-  
flop when the clock is LOW. When the clock transitions from LOW to HIGH, the data in the master section  
transfers into the slave section and through to the outputs.  
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.  
TRUTH TABLE  
LOGIC DIAGRAM AND PINOUT ASSIGNMENT  
D
S*  
R*  
CLK  
Q
Q¯  
L
H
X
X
X
L
L
H
L
H
L
L
L
H
H
Z
Z
X
X
X
L
H
H
L
H
L
L
H
1
2
3
4
8
V
S
D
CC  
S
Undef Undef  
D
Q
7
6
5
Z = LOW to HIGH Transition  
* Pins will default low when left open  
Flip Flop  
R
PIN DESCRIPTION  
Q
CLK  
R
PIN  
FUNCTION  
Set Input  
Data Input  
S
D
R
V
EE  
Reset Input  
CLK  
Q, Q¯  
VCC  
Clock Input  
Data Outputs  
Positive Supply  
Negative Supply  
VEE  
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541  
www.azmicrotek.com  

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