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AZ10EL16T PDF预览

AZ10EL16T

更新时间: 2024-11-08 04:33:23
品牌 Logo 应用领域
AZM /
页数 文件大小 规格书
6页 80K
描述
ECL/PECL Differential Receiver

AZ10EL16T 技术参数

是否Rohs认证:不符合生命周期:Contact Manufacturer
包装说明:,Reach Compliance Code:compliant
风险等级:5.46Is Samacsys:N
Base Number Matches:1

AZ10EL16T 数据手册

 浏览型号AZ10EL16T的Datasheet PDF文件第2页浏览型号AZ10EL16T的Datasheet PDF文件第3页浏览型号AZ10EL16T的Datasheet PDF文件第4页浏览型号AZ10EL16T的Datasheet PDF文件第5页浏览型号AZ10EL16T的Datasheet PDF文件第6页 
ARIZONA MICROTEK, INC.  
AZ10EL16  
AZ100EL16  
ECL/PECL Differential Receiver  
FEATURES  
PACKAGE AVAILABILITY  
RoHS Compliant / Lead (Pb) Free Package  
Available  
250ps Propagation Delay  
High Bandwidth Output Transitions  
75kΩ Internal Input Pulldown Resistors  
Direct Replacement for ON Semiconductor  
MC10EL16 & MC100EL16  
PACKAGE  
PART NUMBER  
MARKING  
AZM10  
EL16  
AZM100  
EL16  
NOTES  
SOIC 8  
AZ10EL16D  
1,2  
SOIC 8  
AZ100EL16D  
AZ100EL16D+  
1,2  
1,2  
SOIC 8 RoHS  
Compliant /  
Lead (Pb) Free  
AZM100+  
EL16  
TSSOP 8  
AZ10EL16T  
AZ100EL16T  
AZT16T  
AZH16T  
1,2  
1,2  
TSSOP 8  
1
2
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K  
parts) Tape & Reel.  
Date code format: “Y” or “YY” for year followed by “WW” for week on  
underside of part.  
DESCRIPTION  
The AZ10/100EL16 is a differential receiver. The device is functionally equivalent to the E116 device with  
higher performance capabilities. With output transition times significantly faster than the E116, the EL16 is ideally  
suited for interfacing with high frequency sources.  
The EL16 provides a VBB output for either single-ended use or a DC bias reference for AC coupling to the  
device. For single-ended input applications, the VBB reference should be connected to one side of the D/D¯ differential  
input pair. The input signal is then fed to the other D/D¯ input. The VBB pin can support 1.0mA sink/source current.  
When used, the VBB pin should be bypassed to ground via a 0.01μF capacitor.  
Under open input conditions (pulled to VEE) internal input clamps will force the Q output LOW.  
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.  
LOGIC DIAGRAM AND PINOUT ASSIGNMENT  
PIN DESCRIPTION  
1
2
3
4
8
VCC  
NC  
PIN  
D, D¯  
Q, Q¯  
VBB  
VCC  
VEE  
NC  
FUNCTION  
Data Inputs  
Data Outputs  
Reference Voltage Output  
Positive Supply  
Negative Supply  
No Connect  
Q
7
6
5
D
D
Q
VEE  
VBB  
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541  
www.azmicrotek.com  

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