Datasheet > AZ10E142

AZ10E142

更新时间： 2024-11-08 04:33:23

品牌	Logo	应用领域
AZM		移位寄存器
页数	文件大小	规格书
5页	75K
描述
ECL/PECL 9-bit Shift Register

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数据手册

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AZ10E142 数据手册

ARIZONA MICROTEK, INC.

AZ10E142

AZ100E142

ECL/PECL 9-bit Shift Register

FEATURES

PACKAGE AVAILABILITY

•

700 MHz Minimum Shift Frequency

9-Bit for Byte-Parity Application

Asynchronous Master Reset

Dual Clocks

Operating Range of 4.2V to 5.46V

75kΩ Internal Input Pulldown Resistors

Direct Replacement for ON Semi

MC10E142 & MC100E142

PACKAGE

PART NUMBER

MARKING

NOTES

AZM10E142

AZM100E142

PLCC 28

AZ10E142FN

1,2

PLCC 28

AZ100E142FN

1,2

Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.

Date code format: “YY” for year followed by “WW” for week.

DESCRIPTION

The AZ10/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs

serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data,

while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function.

To minimize noise and power, any Q output not used should be left unterminated.

The SEL (Select) input pin is used to switch between the two modes of operation – SHIFT and LOAD. The shift

direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of

CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR)

asynchronously resets all the registers to zero.

NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

V_CCO

SEL

CLK1

CLK2

V_CC

V_EE

Pinout: 28-lead

PLCC (top view)

V_CCO

S-IN

V_CCO

1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541

www.azmicrotek.com

12 3 4 5

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