Datasheet > AZ10E131

AZ10E131

更新时间： 2024-11-08 04:33:23

品牌	Logo	应用领域
AZM		触发器
页数	文件大小	规格书
6页	76K
描述
ECL/PECL 4-bit D Flip-Flop

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数据手册

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AZ10E131 数据手册

ARIZONA MICROTEK, INC.

AZ10E131

AZ100E131

ECL/PECL 4-bit D Flip-Flop

FEATURES

PACKAGE AVAILABILITY

•

1100 MHz Min. Toggle Frequency

Differential Outputs

Individual and Common Clocks

Individual Resets (asynchronous)

Paired Sets (asynchronous)

Operating Range of 4.2V to 5.46V

75kΩ Internal Input Pulldown Resistors

Direct Replacement for On Semiconductor

MC10E131 & MC100E131

PACKAGE

PART NUMBER

MARKING

NOTES

AZM10E131

AZM100E131

PLCC 28

AZ10E131FN

1,2

PLCC 28

AZ100E131FN

1,2

Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.

Date code format: “YY” for year followed by “WW” for week.

DESCRIPTION

The AZ10/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be

clocked separately by holding Common Clock (C_C) LOW and using the Clock Enable (C¯¯En) inputs for clocking.

Common clocking is achieved by holding the C¯¯En inputs LOW and using C_Cto clock all four flip-flops. In this

case, the C¯¯En inputs perform the function of controlling the common clock to each flip-flop.

Individual asynchronous resets are provided (Rn). Asynchronous set controls (Sn) are ganged together in pairs,

with the pairing chosen to reflect physical chip symmetry.

Data enters the master when both C_Cand C¯¯En are LOW, and transfers to the slave when either C_Cor C¯¯En (or

both) go HIGH.

NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

CE2

V_CCO

CE3

V_CC

S12

V_EE

C_C

Pinout: 28-Lead

PLCC (top view)

S03

CE0

CE1

V_CCO

* All V_CCand V_CCOpins are tied together on the die.

1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541

www.azmicrotek.com

12 3 4 5 6

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