Datasheet > AZ10E116

AZ10E116

更新时间： 2024-11-10 04:33:23

品牌	Logo	应用领域
AZM		/
页数	文件大小	规格书
5页	79K
描述
ECL/PECL Quint Differential Line Receiver

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AZ10E116 数据手册

ARIZONA MICROTEK, INC.

AZ10E116

AZ100E116

ECL/PECL Quint Differential Line Receiver

FEATURES

PACKAGE AVAILABILITY

•

500ps Maximum Propagation Delay

Dedicated V_CCOPin for Each Receiver

Operating Range of 4.2V to 5.46V

75kΩ Internal Input Pulldown Resistors

Direct Replacement for ON Semiconductor

MC10E116 & MC100E116

PACKAGE

PART NUMBER

MARKING

NOTES

AZM10E116

AZM100E116

PLCC 28

AZ10E116FN

1,2

PLCC 28

AZ100E116FN

1,2

Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.

Date code format: “YY” for year followed by “WW” for week.

DESCRIPTION

The AZ10/100E116 is a quint differential line receiver with emitter-follower outputs. The E116 provides a V_BB

output for single-ended use or a DC bias reference for AC coupling to the device. For single-ended input

applications, the V_BBreference should be connected to one side of the Dn/D¯n differential input pair. The input

signal is then fed to the other Dn/D¯n input. The V_BBpin should be used only as a bias for the E116 as its sink/source

capability is limited. When used, the V_BBpin should be bypassed to ground via a 0.01μF capacitor.

The receiver design features clamp circuitry to cause a defined state if both the inverting and non-inverting

inputs are left open; in this case the Q output goes LOW, while the Q¯ output goes HIGH. This feature makes the

device ideal for twisted pair applications.

If both inverting and non-inverting inputs are at an equal potential of > V_CC-2.5V, the receiver does not go

to a defined state. This condition may produce output voltage levels between HIGH and LOW.

NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541

www.azmicrotek.com

12 3 4 5

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