Datasheet > AZ10E111FN

AZ10E111FN

更新时间： 2024-11-08 04:33:23

品牌	Logo	应用领域
AZM		时钟驱动器
页数	文件大小	规格书
6页	92K
描述
ECL/PECL 1:9 Differential Clock Driver

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AZ10E111FN 技术参数

是否Rohs认证：	不符合	生命周期：	Contact Manufacturer
包装说明：	QCCJ, LDCC28,.5SQ	Reach Compliance Code：	compliant
风险等级：	5.88	Is Samacsys：	N
JESD-30 代码：	S-PQCC-J28	JESD-609代码：	e0
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC28,.5SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
电源：	-5.2 V	Prop。Delay @ Nom-Sup：	0.9 ns
认证状态：	Not Qualified	子类别：	Clock Drivers
表面贴装：	YES	技术：	ECL10K
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	Base Number Matches：	1

AZ10E111FN 数据手册

ARIZONA MICROTEK, INC.

AZ10E111

AZ100E111

ECL/PECL 1:9 Differential Clock Driver

FEATURES

PACKAGE AVAILABILITY

•

Low Skew

Differential Design

Clock Enable

V_BBOutput

Operating Range of 4.2V to 5.46V

75kΩ Internal Input Pulldown Resistors

Direct Replacement for ON Semi

MC10E111 & MC100E111

PACKAGE

PART NUMBER

MARKING

NOTES

AZM10E111

AZM100E111

PLCC 28

AZ10E111FN

1,2

PLCC 28

AZ100E111FN

1,2

Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.

Date code format: “YY” for year followed by “WW” for week.

DESCRIPTION

The AZ10/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN

signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the

device by forcing all Q outputs LOW and all Q¯ outputs HIGH.

The AZ100E111 provides a V_BBoutput for single-ended use or a DC bias reference for AC coupling to the

device. For single–ended input applications, the V_BBreference should be connected to one side of the IN/I¯N¯

differential input pair. The input signal is then fed to the other IN/I¯N¯ input. The V_BBpin should be used only as a

bias for the E111 as its sink/source capability is limited. When used, the V_BBpin should be bypassed to ground via a

0.01μF capacitor.

The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and

layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process

control limits that ensure consistent t_pddistributions from lot-to-lot. The net result is a dependable, low skew device.

To ensure that the tight skew specification is met, both sides of the differential output must be terminated into

50Ω, even if only one side is used. In most applications all nine differential pairs will be used and therefore

terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on

the same package side (i.e. sharing the same V_CCO) as the pair(s) being used on that side, in order to maintain

minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of

the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin.

NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.

1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541

www.azmicrotek.com

12 3 4 5 6

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