Datasheet > AZ100LVEL33_11

AZ100LVEL33_11

更新时间： 2024-09-19 07:16:15

品牌	Logo	应用领域
AZM		/
页数	文件大小	规格书
8页	107K
描述
ECL/PECL ÷4 Divider

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数据手册

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AZ100LVEL33_11 数据手册

ARIZONA MICROTEK, INC.

AZ100LVEL33

ECL/PECL ÷4 Divider

PACKAGE AVAILABILITY

FEATURES

PACKAGE

PART NUMBER

MARKING NOTES



Green / RoHS Compliant /

MLP 8 (2x2) Green

/ RoHS Compliant /

Lead (Pb) Free

SOIC 8 Green /

RoHS Compliant /

Lead (Pb) Free

MSOP 8 Green /

RoHS Compliant /

Lead (Pb) Free

C3G

Lead (Pb) Free package available

Operating Range of 3.0V to 5.5V

470ps Propagation Delay

5.0+ GHz Toggle Frequency

Internal Input Pulldown Resistors

Direct Replacement for ON Semiconductor

MC100EL33 & MC100LVEL33

Transistor Count = 91 Devices

IBIS Model Files Available on Arizona

Microtek Web Site

AZ100LVEL33NG

AZ100LVEL33DG

AZ100LVEL33TG

1,2



AZM100G

1,2,3

LVEL33

AZHG

1,2,3

LV33



Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K

parts) Tape & Reel.

Date code format: “Y” or “YY” for year followed by “WW” for week.

Date code “YWW” or “YYWW” on underside of part.



>2 kV HBM ESD Protection

Additional ESD Data Available on

Arizona Microtek Website

DESCRIPTION

The AZ100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low,

Q¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for

the synchronization of multiple LVEL33’s in a system.

The LVEL33 provides a V_BBoutput for single-end use or a DC bias reference for AC coupling to the device.

For single-ended input applications, the V_BBreference should be connected to one side of the CLK/C¯¯L¯K¯ differential

input pair. The input signal is then fed to the other CLK/C¯¯L¯K¯ input. The V_BBpin can support 1.0mA sink/source

current. When used, the V_BBpin should be bypassed to ground via a 0.01F capacitor.

NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.

LOGIC DIAGRAM

PIN DESCRIPTION

RESET

FUNCTION

CLK, C¯L¯¯K Clock Inputs

RESET

V_BB

Q, Q¯

V_CC

Asynchronous Reset

Reference Voltage Output

Data Outputs

÷4

CLK

Positive Supply

V_EE

Negative Supply

V_BB

1630 S. STAPLEY DR., SUITE 127  MESA, ARIZONA 85204  USA  (480) 962-5881  FAX (623) 505-2414

www.azmicrotek.com

12 3 4 5 6 7 8

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